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2022-09-13target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell
The riscv target incorrectly enabled semihosting always, whether the user asked for it or not. Call semihosting_enabled() passing the correct value to the is_userspace argument, which fixes this and also handles the userspace=on argument. Because we do this at translate time, we no longer need to check the privilege level in riscv_cpu_do_interrupt(). Note that this is a behaviour change: we used to default to semihosting being enabled, and now the user must pass "-semihosting-config enable=on" if they want it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220822141230.3658237-8-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-07target/riscv: Add few cache related PMU eventsAtish Patra
Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221701.41932-4-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Add vstimecmp supportAtish Patra
vstimecmp CSR allows the guest OS or to program the next guest timer interrupt directly. Thus, hypervisor no longer need to inject the timer interrupt to the guest if vstimecmp is used. This was ratified as a part of the Sstc extension. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221357.41070-4-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel
The arch review of AIA spec is completed and we now have official extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode AIA CSRs). Refer, section 1.6 of the latest AIA v0.3.1 stable specification at https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32/riscv-interrupts-032.pdf) Based on above, we update QEMU RISC-V to: 1) Have separate config options for Smaia and Ssaia extensions which replace RISCV_FEATURE_AIA in CPU features 2) Not generate AIA INTC compatible string in virt machine Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220820042958.377018-1-apatel@ventanamicro.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen
According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s". There are multiple possibility for agnostic elements according to v-spec. The main intent of this patch-set tries to add option that can distinguish between mask policies. Setting agnostic elements to all 1s allows QEMU to express this. This is the first commit regarding the optional mask agnostic behavior. Follow-up commits will add this optional behavior for all rvv instructions. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165570784143.17634.35095816584573691-1@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()Anup Patel
We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Acked-by: dramforever <dramforever@live.com> Message-Id: <20220630061150.905174-2-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03target/riscv: Update default priority table for local interruptsAnup Patel
The latest AIA draft v0.3.0 defines a relatively simpler scheme for default priority assignments where: 1) local interrupts 24 to 31 and 48 to 63 are reserved for custom use and have implementation specific default priority. 2) remaining local interrupts 0 to 23 and 32 to 47 have a recommended (not mandatory) priority assignments. We update the default priority table and hviprio mapping as-per above. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220616031543.953776-3-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-28semihosting: Return void from do_common_semihostingRichard Henderson
Perform the cleanup in the FIXME comment in common_semi_gdb_syscall. Do not modify guest registers until the syscall is complete, which in the gdbstub case is asynchronous. In the synchronous non-gdbstub case, use common_semi_set_ret to set the result. Merge set_swi_errno into common_semi_cb. Rely on the latter for combined return value / errno setting. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD
According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". There are multiple possibility for agnostic elements according to v-spec. The main intent of this patch-set tries to add option that can distinguish between tail policies. Setting agnostic elements to all 1s allows QEMU to express this. This is the first commit regarding the optional tail agnostic behavior. Follow-up commits will add this optional behavior for all rvv instructions. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-5@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-10target/riscv: Wake on VS-level external interruptsAndrew Bresticker
Whether or not VSEIP is pending isn't reflected in env->mip and must instead be determined from hstatus.vgein and hgeip. As a result a CPU in WFI won't wake on a VSEIP, which violates the WFI behavior as specified in the privileged ISA. Just use riscv_cpu_all_pending() instead, which already accounts for VSEIP. Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220531210544.181322-1-abrestic@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel
Currently, the [m|s]tval CSRs are set with trapping instruction encoding only for illegal instruction traps taken at the time of instruction decoding. In RISC-V world, a valid instructions might also trap as illegal or virtual instruction based to trapping bits in various CSRs (such as mstatus.TVM or hstatus.VTVM). We improve setting of [m|s]tval CSRs for all types of illegal and virtual instruction traps. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220511144528.393530-4-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-05-24target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-modeAnup Patel
Currently, QEMU does not set hstatus.GVA bit for traps taken from HS-mode into HS-mode which breaks the Xvisor nested MMU test suite on QEMU. This was working previously. This patch updates riscv_cpu_do_interrupt() to fix the above issue. Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220511144528.393530-3-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-22hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang
RISC-V privilege spec defines that mtime is exposed as a memory-mapped machine-mode read-write register. However, as QEMU uses host monotonic timer as timer source, this makes mtime to be read-only in RISC-V ACLINT. This patch makes mtime to be writable by recording the time delta value between the mtime value to be written and the timer value at the time mtime is written. Time delta value is then added back whenever the timer value is retrieved. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220420080901.14655-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-22target/riscv: Use cpu_loop_exit_restore directly from mmu faultsRichard Henderson
The riscv_raise_exception function stores its argument into exception_index and then exits to the main loop. When we have already set exception_index, we can just exit directly. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220401125948.79292-2-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li
Co-authored-by: ardxwe <ardxwe@gmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220211043920.28981-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-16target/riscv: add support for svpbmt extensionWeiwei Li
- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently - add PTE_PBMT bit check for inner PTE Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220204022658.18097-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-16target/riscv: add support for svnapot extensionWeiwei Li
- add PTE_N bit - add PTE_N bit check for inner PTE - update address translation to support 64KiB continuous region (napot_bits = 4) Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220204022658.18097-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-16target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTEWeiwei Li
For non-leaf PTEs, the D, A, and U bits are reserved for future standard use. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220204022658.18097-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-16target/riscv: Ignore reserved bits in PTE for RV64Guo Ren
Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual-Memory System 2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220204022658.18097-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel
The AIA specification adds new CSRs for RV32 so that RISC-V hart can support 64 local interrupts on both RV32 and RV64. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-11-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel
The AIA spec defines programmable 8-bit priority for each local interrupt at M-level, S-level and VS-level so we extend local interrupt processing to consider AIA interrupt priorities. The AIA CSRs which help software configure local interrupt priorities will be added by subsequent patches. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220204174700.534953-10-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-16target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel
The AIA device emulation (such as AIA IMSIC) should be able to set (or provide) AIA ireg read-modify-write callback for each privilege level of a RISC-V HART. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-9-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-16target/riscv: Improve delivery of guest external interruptsAnup Patel
The guest external interrupts from an interrupt controller are delivered only when the Guest/VM is running (i.e. V=1). This means any guest external interrupt which is triggered while the Guest/VM is not running (i.e. V=0) will be missed on QEMU resulting in Guest with sluggish response to serial console input and other I/O events. To solve this, we check and inject interrupt after setting V=1. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-5-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel
The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-4-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei
We need not specially process vtype when XLEN changes. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Split pm_enabled into mask and baseLIU Zhiwei
Use cached cur_pmmask and cur_pmbase to infer the current PM mode. This may decrease the TCG IR by one when pm_enabled is true and pm_base_enabled is false. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-15-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220120122050.41546-12-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Ignore the pc bits above XLENLIU Zhiwei
The read from PC for translation is in cpu_get_tb_cpu_state, before translation. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-7-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Create xl field in envLIU Zhiwei
Current xlen has been used in helper functions and many other places. The computation of current xlen is not so trivial, so that we should recompute it as little as possible. Fortunately, xlen only changes in very seldom cases, such as exception, misa write, mstatus write, cpu reset, migration load. So that we can only recompute xlen in this places and cache it into CPURISCVState. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-6-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-12-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-2-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis
The stval and mtval registers can optionally contain the faulting instruction on an illegal instruction exception. This patch adds support for setting the stval and mtval registers. The RISC-V spec states that "The stval register can optionally also be used to return the faulting instruction bits on an illegal instruction exception...". In this case we are always writing the value on an illegal instruction. This doesn't match all CPUs (some CPUs won't write the data), but in QEMU let's just populate the value on illegal instructions. This won't break any guest software, but will provide more information to guests. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211220064916.107241-4-alistair.francis@opensource.wdc.com
2022-01-08target/riscv: Fixup setting GVAAlistair Francis
In preparation for adding support for the illegal instruction address let's fixup the Hypervisor extension setting GVA logic and improve the variable names. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211220064916.107241-3-alistair.francis@opensource.wdc.com
2021-12-20target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 1.0. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-27-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-8-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211210075704.23951-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-11-02target/riscv: Make riscv_cpu_tlb_fill sysemu onlyRichard Henderson
The fallback code in cpu_loop_exit_sigsegv is sufficient for riscv linux-user. Remove the code from cpu_loop that raised SIGSEGV. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-29target/riscv: remove force HS exceptionJose Martins
There is no need to "force an hs exception" as the current privilege level, the state of the global ie and of the delegation registers should be enough to route the interrupt to the appropriate privilege level in riscv_cpu_do_interrupt. The is true for both asynchronous and synchronous exceptions, specifically, guest page faults which must be hardwired to zero hedeleg. As such the hs_force_except mechanism can be removed. Signed-off-by: Jose Martins <josemartins90@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211026145126.11025-3-josemartins90@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-29target/riscv: fix VS interrupts forwarding to HSJose Martins
VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when not delegated in hideleg (which was not being taken into account). This was mainly because hs level sie was not always considered enabled when it should. The spec states that "Interrupts for higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE bit for the higher-privilege mode." and also "For purposes of interrupt global enables, HS-mode is considered more privileged than VS-mode, and VS-mode is considered more privileged than VU-mode". Also, vs-level interrupts were not being taken into account unless V=1, but should be unless delegated. Finally, there is no need for a special case for to handle vs interrupts as the current privilege level, the state of the global ie and of the delegation registers should be enough to route all interrupts to the appropriate privilege level in riscv_cpu_do_interrupt. Signed-off-by: Jose Martins <josemartins90@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211026145126.11025-2-josemartins90@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-28target/riscv: Implement address masking functions required for RISC-V ↵Anatoly Parshintsev
Pointer Masking extension Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211025173609.2724490-8-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson
The position of this read-only field is dependent on the current xlen. Rather than having to compute that difference in many places, compute it only on read. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-16-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson
Begin adding support for switching XLEN at runtime. Extract the effective XLEN from MISA and MSTATUS and store for use during translation. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-6-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson
Shortly, the set of supported XL will not be just 32 and 64, and representing that properly using the enumeration will be imperative. Two places, booting and gdb, intentionally use misa_mxl_max to emphasize the use of the reset value of misa.mxl, and not the current cpu state. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-5-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson
Move the function to cpu_helper.c, as it is large and growing. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-2-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-21target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang
When virtual registers are swapped, mstatus.SD bit should also be backed up/restored. Otherwise, mstatus.SD bit will be incorrectly kept across the world switches. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210914013717.881430-1-frank.chang@sifive.com [ Changes by AF: - Convert variable to a uint64_t to fix clang error ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-14target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé
Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20210911165434.531552-19-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com
2021-05-11target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com
2021-05-11target/riscv: fix exception index on instruction access faultEmmanuel Blot
When no MMU is used and the guest code attempts to fetch an instruction from an invalid memory location, the exception index defaults to a data load access fault, rather an instruction access fault. Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: FB9EA197-B018-4879-AB0F-922C2047A08B@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-11riscv: don't look at SUM when accessing memory from a debugger contextJade Fink
Previously the qemu monitor and gdbstub looked at SUM and refused to perform accesses to user memory if it is off, which was an impediment to debugging. Signed-off-by: Jade Fink <qemu@jade.fyi> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210406113109.1031033-1-qemu@jade.fyi Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-18 01:15:10 +0000