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path: root/target/riscv/cpu_helper.c
AgeCommit message (Expand)Author
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis
2022-01-08target/riscv: Fixup setting GVAAlistair Francis
2021-12-20target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang
2021-12-20target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei
2021-11-02target/riscv: Make riscv_cpu_tlb_fill sysemu onlyRichard Henderson
2021-10-29target/riscv: remove force HS exceptionJose Martins
2021-10-29target/riscv: fix VS interrupts forwarding to HSJose Martins
2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson
2021-10-22target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson
2021-09-21target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang
2021-09-14target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis
2021-05-11target/riscv: fix exception index on instruction access faultEmmanuel Blot
2021-05-11riscv: don't look at SUM when accessing memory from a debugger contextJade Fink
2021-05-11target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra
2021-03-22target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer
2021-03-22target/riscv: Use background registers also for MSTATUS_MPVGeorg Kotheimer
2021-03-22target/riscv: Adjust privilege level for HLV(X)/HSV instructionsGeorg Kotheimer
2021-03-22target/riscv: add log of PMP permission checkingJim Shu
2021-03-22target/riscv: propagate PMP permission to TLB pageJim Shu
2021-03-10semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana
2021-01-18riscv: Add semihosting supportKeith Packard
2020-12-17target/riscv: cpu_helper: Remove compile time XLEN checksAlistair Francis
2020-12-17target/riscv: Fix the bug of HLVX/HLV/HSVYifei Jiang
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis
2020-11-09target/riscv: Add a virtualised MMU ModeAlistair Francis
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang
2020-10-22target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang
2020-10-22target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interruptGeorg Kotheimer
2020-10-22target/riscv: Fix update of hstatus.SPVPGeorg Kotheimer
2020-10-22riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis
2020-09-23qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng
2020-09-09target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis
2020-08-25target/riscv: Fix the interrupt cause codeAlistair Francis
2020-08-25target/riscv: Convert MSTATUS MTL to GVAAlistair Francis
2020-08-25target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructionsAlistair Francis
2020-08-25target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis
2020-08-21target/riscv: Change the TLB page size depends on PMP entries.Zong Li
2020-08-21target/riscv: Fix the translation of physical addressZong Li
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