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path: root/target/riscv/cpu_helper.c
AgeCommit message (Expand)Author
2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé
2023-01-06Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qem...Peter Maydell
2023-01-06target/riscv: support cache-related PMU events in virtual modeJim Shu
2023-01-06target/riscv: Add itrigger_enabled field to CPURISCVStateLIU Zhiwei
2023-01-06target/riscv: Add itrigger support when icount is enabledLIU Zhiwei
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei
2023-01-06target/riscv: Fix PMP propagation for tlbLIU Zhiwei
2023-01-04target/riscv: Use QEMU_IOTHREAD_LOCK_GUARD in riscv_cpu_update_mipRichard Henderson
2022-09-13target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell
2022-09-07target/riscv: Add few cache related PMU eventsAtish Patra
2022-09-07target/riscv: Add vstimecmp supportAtish Patra
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()Anup Patel
2022-07-03target/riscv: Update default priority table for local interruptsAnup Patel
2022-06-28semihosting: Return void from do_common_semihostingRichard Henderson
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD
2022-06-10target/riscv: Wake on VS-level external interruptsAndrew Bresticker
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel
2022-05-24target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-modeAnup Patel
2022-04-22hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang
2022-04-22target/riscv: Use cpu_loop_exit_restore directly from mmu faultsRichard Henderson
2022-03-03target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li
2022-02-16target/riscv: add support for svpbmt extensionWeiwei Li
2022-02-16target/riscv: add support for svnapot extensionWeiwei Li
2022-02-16target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTEWeiwei Li
2022-02-16target/riscv: Ignore reserved bits in PTE for RV64Guo Ren
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel
2022-02-16target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel
2022-02-16target/riscv: Improve delivery of guest external interruptsAnup Patel
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei
2022-01-21target/riscv: Split pm_enabled into mask and baseLIU Zhiwei
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei
2022-01-21target/riscv: Ignore the pc bits above XLENLIU Zhiwei
2022-01-21target/riscv: Create xl field in envLIU Zhiwei
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis
2022-01-08target/riscv: Fixup setting GVAAlistair Francis
2021-12-20target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang
2021-12-20target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei
2021-11-02target/riscv: Make riscv_cpu_tlb_fill sysemu onlyRichard Henderson
2021-10-29target/riscv: remove force HS exceptionJose Martins
2021-10-29target/riscv: fix VS interrupts forwarding to HSJose Martins
2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson
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