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path: root/target/riscv/cpu_helper.c
AgeCommit message (Expand)Author
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis
2021-05-11target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis
2021-05-11target/riscv: fix exception index on instruction access faultEmmanuel Blot
2021-05-11riscv: don't look at SUM when accessing memory from a debugger contextJade Fink
2021-05-11target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra
2021-03-22target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer
2021-03-22target/riscv: Use background registers also for MSTATUS_MPVGeorg Kotheimer
2021-03-22target/riscv: Adjust privilege level for HLV(X)/HSV instructionsGeorg Kotheimer
2021-03-22target/riscv: add log of PMP permission checkingJim Shu
2021-03-22target/riscv: propagate PMP permission to TLB pageJim Shu
2021-03-10semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana
2021-01-18riscv: Add semihosting supportKeith Packard
2020-12-17target/riscv: cpu_helper: Remove compile time XLEN checksAlistair Francis
2020-12-17target/riscv: Fix the bug of HLVX/HLV/HSVYifei Jiang
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis
2020-11-09target/riscv: Add a virtualised MMU ModeAlistair Francis
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang
2020-10-22target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang
2020-10-22target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interruptGeorg Kotheimer
2020-10-22target/riscv: Fix update of hstatus.SPVPGeorg Kotheimer
2020-10-22riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis
2020-09-23qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng
2020-09-09target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis
2020-08-25target/riscv: Fix the interrupt cause codeAlistair Francis
2020-08-25target/riscv: Convert MSTATUS MTL to GVAAlistair Francis
2020-08-25target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructionsAlistair Francis
2020-08-25target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis
2020-08-21target/riscv: Change the TLB page size depends on PMP entries.Zong Li
2020-08-21target/riscv: Fix the translation of physical addressZong Li
2020-06-19target/riscv: Report errors validating 2nd-stage PTEsAlistair Francis
2020-06-19target/riscv: Set access as data_load when validating stage-2 PTEsAlistair Francis
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis
2020-04-29riscv: Fix Stage2 SV32 page table walkAnup Patel
2020-04-29riscv: AND stage-1 and stage-2 protection flagsAlistair Francis
2020-04-29riscv: Don't use stage-2 PTE lookup protection flagsAlistair Francis
2020-03-16target/riscv: Fix VS mode interrupts forwarding.Rajnesh Kanwal
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis
2020-02-27target/riscv: Set htval and mtval2 on execptionsAlistair Francis
2020-02-27target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis
2020-02-27target/riscv: Implement second stage MMUAlistair Francis
2020-02-27target/riscv: Allow specifying MMU stageAlistair Francis
2020-02-27target/riscv: Disable guest FP support based on virtual statusAlistair Francis
2020-02-27target/riscv: Add hypvervisor trap supportAlistair Francis
2020-02-27target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis
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