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path: root/target/riscv/cpu_helper.c
AgeCommit message (Expand)Author
2020-06-19target/riscv: Report errors validating 2nd-stage PTEsAlistair Francis
2020-06-19target/riscv: Set access as data_load when validating stage-2 PTEsAlistair Francis
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis
2020-04-29riscv: Fix Stage2 SV32 page table walkAnup Patel
2020-04-29riscv: AND stage-1 and stage-2 protection flagsAlistair Francis
2020-04-29riscv: Don't use stage-2 PTE lookup protection flagsAlistair Francis
2020-03-16target/riscv: Fix VS mode interrupts forwarding.Rajnesh Kanwal
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis
2020-02-27target/riscv: Set htval and mtval2 on execptionsAlistair Francis
2020-02-27target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis
2020-02-27target/riscv: Implement second stage MMUAlistair Francis
2020-02-27target/riscv: Allow specifying MMU stageAlistair Francis
2020-02-27target/riscv: Disable guest FP support based on virtual statusAlistair Francis
2020-02-27target/riscv: Add hypvervisor trap supportAlistair Francis
2020-02-27target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis
2020-02-27target/riscv: Add support for virtual interrupt settingAlistair Francis
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis
2020-02-27target/riscv: Add the force HS exception modeAlistair Francis
2020-02-27target/riscv: Add the virtulisation modeAlistair Francis
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé
2019-11-14target/riscv: Remove atomic accesses to MIP CSRAlistair Francis
2019-10-28linux-user/riscv: Propagate fault addressGiuseppe Musacchio
2019-10-28RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt
2019-10-28RISC-V: Handle bus errors in the page table walkerPalmer Dabbelt
2019-09-17riscv: rv32: Root page table address can be larger than 32-bitBin Meng
2019-09-17target/riscv: Create function to test if FP is enabledAlistair Francis
2019-06-25RISC-V: Clear load reservations on context switch and SCJoel Sing
2019-06-23RISC-V: Fix a PMP check with the correct access sizeHesham Almatary
2019-06-23RISC-V: Check PMP during Page Table WalksHesham Almatary
2019-06-23RISC-V: Check for the effective memory privilege mode during PMP checksHesham Almatary
2019-06-23RISC-V: Raise access fault exceptions on PMP violationsHesham Almatary
2019-06-23RISC-V: Only Check PMP if MMU translation succeedsHesham Almatary
2019-06-23target/riscv: Implement riscv_cpu_unassigned_accessMichael Clark
2019-06-10target/riscv: Use env_cpu, env_archcpuRichard Henderson
2019-05-24target/riscv: Improve the scause logicAlistair Francis
2019-05-24target/riscv: Trigger interrupt on MIP update asynchronouslyAlistair Francis
2019-05-10tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson
2019-05-10target/riscv: Convert to CPUClass::tlb_fillRichard Henderson
2019-03-19RISC-V: Update load reservation comment in do_interruptMichael Clark
2019-03-19RISC-V: Convert trap debugging to trace eventsMichael Clark
2019-03-19RISC-V: Add support for vectored interruptsMichael Clark
2019-03-19RISC-V: Change local interrupts from edge to levelMichael Clark
2019-03-19RISC-V: Allow interrupt controllers to claim interruptsMichael Clark
2019-02-11RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark
2019-01-09RISC-V: Implement existential predicates for CSRsMichael Clark
2019-01-08RISC-V: Implement modular CSR helper interfaceMichael Clark
2018-12-20RISC-V: Add hartid and \n to interrupt loggingMichael Clark
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