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path: root/target/riscv/cpu_bits.h
AgeCommit message (Expand)Author
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis
2020-02-27target/riscv: Add the force HS exception modeAlistair Francis
2020-02-27target/riscv: Add the virtulisation modeAlistair Francis
2020-02-27target/riscv: Rename the H irqs to VS irqsAlistair Francis
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis
2020-02-27target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis
2019-09-17target/riscv: Update the Hypervisor CSRs to v0.4Alistair Francis
2019-06-25target/riscv: Add the mcountinhibit CSRAlistair Francis
2019-06-12Supply missing header guardsMarkus Armbruster
2019-05-24target/riscv: Add the HGATP register masksAlistair Francis
2019-05-24target/riscv: Add the HSTATUS register masksAlistair Francis
2019-05-24target/riscv: Add Hypervisor CSR macrosAlistair Francis
2019-05-24target/riscv: Add the MPV and MTL mstatus bitsAlistair Francis
2019-05-24target/riscv: Mark privilege level 2 as reservedAlistair Francis
2019-03-19RISC-V: Fixes to CSR_* register macros.Jim Wilson
2019-02-11RISC-V: Add misa runtime write supportMichael Clark
2018-10-17RISC-V: Update CSR and interrupt definitionsMichael Clark
2018-09-04RISC-V: Improve page table walker spec complianceMichael Clark
2018-03-07RISC-V CPU Core DefinitionMichael Clark
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