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path: root/target/riscv/cpu.h
AgeCommit message (Expand)Author
2023-11-07target/riscv: add riscv_cpu_accelerator_compatible()Daniel Henrique Barboza
2023-11-07target/riscv/tcg: add tcg_cpu_finalize_features()Daniel Henrique Barboza
2023-11-07target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal
2023-11-07target/riscv: Add M-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal
2023-11-07target/riscv: Split interrupt logic from riscv_cpu_update_mip.Rajnesh Kanwal
2023-10-12target/riscv: deprecate capital 'Z' CPU propertiesDaniel Henrique Barboza
2023-10-12target/riscv: add riscv_cpu_get_name()Daniel Henrique Barboza
2023-10-12target/riscv/cpu: move priv spec functions to tcg-cpu.cDaniel Henrique Barboza
2023-10-12target/riscv/cpu.c: export isa_edata_arr[]Daniel Henrique Barboza
2023-10-12target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.cDaniel Henrique Barboza
2023-10-12target/riscv/tcg: introduce tcg_cpu_instance_init()Daniel Henrique Barboza
2023-10-12target/riscv/cpu.c: export set_misa()Daniel Henrique Barboza
2023-10-12target/riscv/kvm: do not use riscv_cpu_add_misa_properties()Daniel Henrique Barboza
2023-10-12target/riscv: make riscv_add_satp_mode_properties() publicDaniel Henrique Barboza
2023-10-12target/riscv: move riscv_cpu_add_kvm_properties() to kvm.cDaniel Henrique Barboza
2023-10-12target/riscv: move riscv_tcg_ops to tcg-cpu.cDaniel Henrique Barboza
2023-10-12target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.cDaniel Henrique Barboza
2023-10-12target/riscv: introduce TCG AccelCPUClassDaniel Henrique Barboza
2023-10-12target/riscv: make CPUCFG() macro publicDaniel Henrique Barboza
2023-10-03accel/tcg: Move CPUNegativeOffsetState into CPUStateRichard Henderson
2023-09-08riscv: spelling fixesMichael Tokarev
2023-07-10target/riscv/cpu: add misa_ext_info_arr[]Daniel Henrique Barboza
2023-07-10target/riscv: Add additional xlen for address when MPRV=1Weiwei Li
2023-06-28target/riscv: Restrict KVM-specific fields from ArchCPUPhilippe Mathieu-Daudé
2023-06-26target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson
2023-06-13target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.hWeiwei Li
2023-06-13target/riscv: rework write_misa()Daniel Henrique Barboza
2023-06-13target/riscv: add PRIV_VERSION_LATESTDaniel Henrique Barboza
2023-05-05target/riscv: add CPU QOM headerDaniel Henrique Barboza
2023-05-05target/riscv: Introduce mmuidx_2stageRichard Henderson
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu
2023-05-05target/riscv: Add a tb flags field for vstartLIU Zhiwei
2023-05-05target/riscv: Remove mstatus_hs_{fs, vs} from tb_flagsRichard Henderson
2023-05-05target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei
2023-05-05target/riscv: Add a general status enum for extensionsLIU Zhiwei
2023-05-05target/riscv: Extract virt enabled state from tb flagsLIU Zhiwei
2023-05-05target/riscv: Use PRV_RESERVED instead of PRV_HWeiwei Li
2023-05-05target/riscv/cpu.c: redesign register_cpu_props()Daniel Henrique Barboza
2023-05-05target/riscv: add RVG and remove cpu->cfg.ext_gDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_vDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_jDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_hDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_uDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_sDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_mDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_eDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_iDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_fDaniel Henrique Barboza
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