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path: root/target/riscv/cpu.h
AgeCommit message (Expand)Author
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson
2021-10-22target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson
2021-10-22target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang
2021-10-07target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang
2021-10-07target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich
2021-10-07target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich
2021-09-21hw/core: Make do_unaligned_access noreturnRichard Henderson
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson
2021-09-14target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé
2021-06-08target/riscv: rvb: add b-ext version cpu optionFrank Chang
2021-06-08target/riscv: rvb: support and turn on B-extension from command lineKito Cheng
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng
2021-06-08target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng
2021-06-08target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé
2021-05-11target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis
2021-05-11target/riscv: Add a config option for ePMPHou Weiying
2021-05-11target/riscv: Add ePMP CSR access functionsHou Weiying
2021-05-11target/riscv: Add the ePMP featureAlistair Francis
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis
2021-05-11target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis
2021-05-11target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis
2021-05-11target/riscv: Add Shakti C class CPUVijai Kumar K
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra
2021-03-22target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer
2021-03-04target-riscv: support QMP dump-guest-memoryYifei Jiang
2021-03-04target/riscv: Declare csr_ops[] with a known sizeBin Meng
2021-01-16target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng
2021-01-16target/riscv: Add CSR name in the CSR function tableBin Meng
2021-01-16target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng
2020-12-17target/riscv: Add a riscv_cpu_is_32bit() helper functionAlistair Francis
2020-12-17target/riscv: Add a TYPE_RISCV_CPU_BASE CPUAlistair Francis
2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis
2020-11-09target/riscv: Add a virtualised MMU ModeAlistair Francis
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang
2020-10-22target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang
2020-09-18qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost
2020-09-13Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng
2020-09-09target/riscv: cpu: Add a new 'resetvec' propertyBin Meng
2020-09-09target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang
2020-09-09Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost
2020-08-25target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis
2020-07-13target/riscv: fix vill bit index in vtype registerFrank Chang
2020-07-02target/riscv: configure and turn on vector extension from command lineLIU Zhiwei
2020-07-02target/riscv: add vector configure instructionLIU Zhiwei
2020-07-02target/riscv: implementation-defined constant parametersLIU Zhiwei
2020-07-02target/riscv: add vector extension field in CPURISCVStateLIU Zhiwei
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