slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2023-05-05	target/riscv: remove cpu->cfg.ext_s	Daniel Henrique Barboza
2023-05-05	target/riscv: remove cpu->cfg.ext_m	Daniel Henrique Barboza
2023-05-05	target/riscv: remove cpu->cfg.ext_e	Daniel Henrique Barboza
2023-05-05	target/riscv: remove cpu->cfg.ext_i	Daniel Henrique Barboza
2023-05-05	target/riscv: remove cpu->cfg.ext_f	Daniel Henrique Barboza
2023-05-05	target/riscv: remove cpu->cfg.ext_d	Daniel Henrique Barboza
2023-05-05	target/riscv: remove cpu->cfg.ext_c	Daniel Henrique Barboza
2023-05-05	target/riscv: remove cpu->cfg.ext_a	Daniel Henrique Barboza
2023-05-05	target/riscv: Fix lines with over 80 characters	Weiwei Li
2023-05-05	target/riscv: Fix format for comments	Weiwei Li
2023-05-05	target/riscv: Remove riscv_cpu_virt_enabled()	Weiwei Li
2023-05-05	target/riscv: Convert env->virt to a bool env->virt_enabled	LIU Zhiwei
2023-05-05	target/riscv: Add support for Zce	Weiwei Li
2023-05-05	target/riscv: add support for Zcmt extension	Weiwei Li
2023-05-05	target/riscv: add cfg properties for Zc* extension	Weiwei Li
2023-05-05	target/riscv: Simplify type conversion for CPURISCVState	Weiwei Li
2023-03-06	riscv: Introduce satp mode hw capabilities	Alexandre Ghiti
2023-03-06	riscv: Allow user to set the satp mode	Alexandre Ghiti
2023-03-05	target/riscv: implement Zicbom extension	Christoph Muellner
2023-03-05	target/riscv: implement Zicboz extension	Christoph Muellner
2023-03-01	Merge patch series "target/riscv: Add support for Svadu extension"	Palmer Dabbelt
2023-03-01	target/riscv: Add csr support for svadu	Weiwei Li
2023-03-01	target/riscv: Add support for Zicond extension	Weiwei Li
2023-03-01	Merge patch series "target/riscv: Some updates to float point related extensi...	Palmer Dabbelt
2023-03-01	target/riscv: Add cfg properties for Zv* extensions	Weiwei Li
2023-03-01	target/riscv/cpu: remove CPUArchState::features and friends	Daniel Henrique Barboza
2023-03-01	target/riscv: remove RISCV_FEATURE_MMU	Daniel Henrique Barboza
2023-03-01	target/riscv: remove RISCV_FEATURE_PMP	Daniel Henrique Barboza
2023-03-01	target/riscv: remove RISCV_FEATURE_EPMP	Daniel Henrique Barboza
2023-03-01	target/riscv: remove RISCV_FEATURE_DEBUG	Daniel Henrique Barboza
2023-03-01	target/riscv: allow MISA writes as experimental	Daniel Henrique Barboza
2023-03-01	target/riscv: introduce riscv_cpu_cfg()	Daniel Henrique Barboza
2023-02-27	target/riscv/cpu: Move Floating-Point fields closer	Philippe Mathieu-Daudé
2023-02-27	target/cpu: Restrict do_transaction_failed() handlers to sysemu	Philippe Mathieu-Daudé
2023-02-27	target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu	Philippe Mathieu-Daudé
2023-02-07	RISC-V: Adding XTheadFmv ISA extension	Christoph Müllner
2023-02-07	RISC-V: Add initial support for T-Head C906	Christoph Müllner
2023-02-07	RISC-V: Adding T-Head FMemIdx extension	Christoph Müllner
2023-02-07	RISC-V: Adding T-Head MemIdx extension	Christoph Müllner
2023-02-07	RISC-V: Adding T-Head MemPair extension	Christoph Müllner
2023-02-07	RISC-V: Adding T-Head multiply-accumulate instructions	Christoph Müllner
2023-02-07	RISC-V: Adding XTheadCondMov ISA extension	Christoph Müllner
2023-02-07	RISC-V: Adding XTheadBs ISA extension	Christoph Müllner
2023-02-07	RISC-V: Adding XTheadBb ISA extension	Christoph Müllner
2023-02-07	RISC-V: Adding XTheadBa ISA extension	Christoph Müllner
2023-02-07	RISC-V: Adding XTheadSync ISA extension	Christoph Müllner
2023-02-07	RISC-V: Adding XTheadCmo ISA extension	Christoph Müllner
2023-01-20	target/riscv/cpu: set cpu->cfg in register_cpu_props()	Daniel Henrique Barboza
2023-01-20	hw/char: riscv_htif: Move registers from CPUArchState to HTIFState	Bin Meng
2023-01-06	RISC-V: Add Zawrs ISA extension support	Christoph Muellner