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path: root/target/riscv/cpu.h
AgeCommit message (Expand)Author
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot
2022-01-08target/riscv: adding high part of some csrsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit M extensionFrédéric Pétrot
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot
2021-12-20target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang
2021-12-20target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang
2021-12-20target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang
2021-12-20target/riscv: rvv-1.0: add VMA and VTAFrank Chang
2021-12-20target/riscv: rvv-1.0: add fractional LMULFrank Chang
2021-12-20target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei
2021-12-20target/riscv: drop vector 0.7.1 and add 1.0 supportFrank Chang
2021-12-20target/riscv: zfh: implement zfhmin extensionFrank Chang
2021-12-20target/riscv: zfh: half-precision load and storeKito Cheng
2021-10-29target/riscv: remove force HS exceptionJose Martins
2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev
2021-10-28target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo
2021-10-28target/riscv: Add J-extension into RISC-VAlexey Baturo
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson
2021-10-22target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson
2021-10-22target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang
2021-10-07target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang
2021-10-07target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich
2021-10-07target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich
2021-09-21hw/core: Make do_unaligned_access noreturnRichard Henderson
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson
2021-09-14target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé
2021-06-08target/riscv: rvb: add b-ext version cpu optionFrank Chang
2021-06-08target/riscv: rvb: support and turn on B-extension from command lineKito Cheng
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng
2021-06-08target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng
2021-06-08target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé
2021-05-11target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis
2021-05-11target/riscv: Add a config option for ePMPHou Weiying
2021-05-11target/riscv: Add ePMP CSR access functionsHou Weiying
2021-05-11target/riscv: Add the ePMP featureAlistair Francis
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis
2021-05-11target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis
2021-05-11target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis
2021-05-11target/riscv: Add Shakti C class CPUVijai Kumar K
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra
2021-03-22target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer
2021-03-04target-riscv: support QMP dump-guest-memoryYifei Jiang
2021-03-04target/riscv: Declare csr_ops[] with a known sizeBin Meng
2021-01-16target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng
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