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path: root/target/riscv/cpu.h
AgeCommit message (Expand)Author
2022-09-07target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()Anup Patel
2022-07-03target/riscv: Support mcycle/minstret write operationAtish Patra
2022-07-03target/riscv: Add support for hpmcounters/hpmeventsAtish Patra
2022-07-03target/riscv: Implement mcountinhibit CSRAtish Patra
2022-07-03target/riscv: pmu: Make number of counters configurableAtish Patra
2022-07-03target/riscv: pmu: Rename the counters extension to pmuAtish Patra
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD
2022-06-10target/riscv: Wake on VS-level external interruptsAndrew Bresticker
2022-06-10target/riscv: add support for zmmul extension v0.1Weiwei Li
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel
2022-05-24target/riscv: Fix typo of mimpid cpu optionFrank Chang
2022-05-24target/riscv: Add short-isa-string optionTsukasa OI
2022-04-29target/riscv: rvk: add cfg properties for zbk* and zk*Weiwei Li
2022-04-29target/riscv: Support configuarable marchid, mvendorid, mipid CSR valuesFrank Chang
2022-04-22target/riscv: cpu: Add a config option for native debugBin Meng
2022-04-22hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang
2022-04-22target/riscv: Add initial support for the Sdtrig extensionBin Meng
2022-04-22target/riscv: Allow software access to MIP SEIPAlistair Francis
2022-04-22target/riscv: Add *envcfg* CSRs supportAtish Patra
2022-04-22target/riscv: Introduce privilege version field in the CSR ops.Atish Patra
2022-04-22target/riscv: Add the privileged spec version 1.12.0Atish Patra
2022-04-22target/riscv: Define simpler privileged spec version numberingAtish Patra
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau
2022-04-06Move CPU softfloat unions to cpu-float.hMarc-André Lureau
2022-03-06target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé
2022-03-06target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé
2022-03-06target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé
2022-03-03target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}Weiwei Li
2022-02-16target/riscv: add support for svinval extensionWeiwei Li
2022-02-16target/riscv: Ignore reserved bits in PTE for RV64Guo Ren
2022-02-16target/riscv: Allow users to force enable AIA CSRs in HARTAnup Patel
2022-02-16target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel
2022-02-16target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel
2022-02-16target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel
2022-02-16target/riscv: Add AIA cpu featureAnup Patel
2022-02-16target/riscv: Allow setting CPU feature from machine/device emulationAnup Patel
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel
2022-02-16target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich
2022-02-16target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUC...Philipp Tomsich
2022-01-21target/riscv: Remove VILL field in VTYPELIU Zhiwei
2022-01-21target/riscv: Adjust vsetvl according to XLENLIU Zhiwei
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei
2022-01-21target/riscv: Split pm_enabled into mask and baseLIU Zhiwei
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei
2022-01-21target/riscv: Create xl field in envLIU Zhiwei
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang
2022-01-21target/riscv: Add kvm_riscv_get/put_regs_timerYifei Jiang
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