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path: root/target/riscv/cpu.h
AgeCommit message (Expand)Author
2023-03-06riscv: Introduce satp mode hw capabilitiesAlexandre Ghiti
2023-03-06riscv: Allow user to set the satp modeAlexandre Ghiti
2023-03-05target/riscv: implement Zicbom extensionChristoph Muellner
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner
2023-03-01Merge patch series "target/riscv: Add support for Svadu extension"Palmer Dabbelt
2023-03-01target/riscv: Add csr support for svaduWeiwei Li
2023-03-01target/riscv: Add support for Zicond extensionWeiwei Li
2023-03-01Merge patch series "target/riscv: Some updates to float point related extensi...Palmer Dabbelt
2023-03-01target/riscv: Add cfg properties for Zv* extensionsWeiwei Li
2023-03-01target/riscv/cpu: remove CPUArchState::features and friendsDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_MMUDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_EPMPDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_DEBUGDaniel Henrique Barboza
2023-03-01target/riscv: allow MISA writes as experimentalDaniel Henrique Barboza
2023-03-01target/riscv: introduce riscv_cpu_cfg()Daniel Henrique Barboza
2023-02-27target/riscv/cpu: Move Floating-Point fields closerPhilippe Mathieu-Daudé
2023-02-27target/cpu: Restrict do_transaction_failed() handlers to sysemuPhilippe Mathieu-Daudé
2023-02-27target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemuPhilippe Mathieu-Daudé
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner
2023-02-07RISC-V: Add initial support for T-Head C906Christoph Müllner
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBa ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner
2023-01-20target/riscv/cpu: set cpu->cfg in register_cpu_props()Daniel Henrique Barboza
2023-01-20hw/char: riscv_htif: Move registers from CPUArchState to HTIFStateBin Meng
2023-01-06RISC-V: Add Zawrs ISA extension supportChristoph Muellner
2023-01-06target/riscv: Add itrigger_enabled field to CPURISCVStateLIU Zhiwei
2023-01-06target/riscv: Add itrigger support when icount is enabledLIU Zhiwei
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei
2023-01-06target/riscv: Add smstateen supportMayuresh Chitale
2022-12-16target/riscv: Convert to 3-phase resetPeter Maydell
2022-10-06dump: Replace opaque DumpState pointer with a typed oneJanosch Frank
2022-09-27target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRsFrank Chang
2022-09-27target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang
2022-09-27target/riscv: Set the CPU resetvec directlyAlistair Francis
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra
2022-09-07target/riscv: Add vstimecmp supportAtish Patra
2022-09-07target/riscv: Add stimecmp supportAtish Patra
2022-09-07hw/intc: Move mtimer/mtimecmp to aclintAtish Patra
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel
2022-09-07target/riscv: Add Zihintpause supportDao Lu
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen
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