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path: root/target/riscv/cpu.c
AgeCommit message (Expand)Author
2021-01-16target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng
2021-01-16gdb: riscv: Add target descriptionSylvain Pelissier
2021-01-07tcg: Make tb arg to synchronize_from_tb constRichard Henderson
2020-12-17target/riscv: cpu: Set XLEN independently from targetAlistair Francis
2020-12-17target/riscv: cpu: Remove compile time XLEN checksAlistair Francis
2020-12-17target/riscv: Specify the XLEN for CPUsAlistair Francis
2020-12-17target/riscv: Add a riscv_cpu_is_32bit() helper functionAlistair Francis
2020-11-03target/riscv: Add basic vmstate description of CPUYifei Jiang
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang
2020-09-18target/riscv: Set instance_align on RISCVCPU TypeInfoRichard Henderson
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng
2020-09-09target/riscv: cpu: Add a new 'resetvec' propertyBin Meng
2020-09-09target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang
2020-07-02target/riscv: configure and turn on vector extension from command lineLIU Zhiwei
2020-07-02target/riscv: implementation-defined constant parametersLIU Zhiwei
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng
2020-06-19target/riscv: Rename IBEX CPU init routineBin Meng
2020-06-19riscv: Keep the CPU init routine names consistentBin Meng
2020-06-19riscv: Generalize CPU init routine for the imacu CPUBin Meng
2020-06-19riscv: Generalize CPU init routine for the gcsu CPUBin Meng
2020-06-19riscv: Generalize CPU init routine for the base CPUBin Meng
2020-06-08Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-re...Peter Maydell
2020-06-05target/riscv/cpu: Restrict CPU migration to system-modePhilippe Mathieu-Daudé
2020-06-03target/riscv: Add the lowRISC Ibex CPUAlistair Francis
2020-06-03target/riscv: Don't set PMP feature in the cpu initAlistair Francis
2020-06-03target/riscv: Disable the MMU correctlyAlistair Francis
2020-06-03target/riscv: Don't overwrite the reset vectorAlistair Francis
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis
2020-06-03target/riscv: Remove the deprecated CPUsAlistair Francis
2020-04-29target/riscv: Add a sifive-e34 cpu typeCorey Wharton
2020-03-17cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell
2020-03-05RISC-V: Add a missing "," in riscv_excp_namesPalmer Dabbelt
2020-02-27target/riscv: Allow enabling the Hypervisor extensionAlistair Francis
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis
2020-02-27target/riscv: Dump Hypervisor registers if enabledAlistair Francis
2020-02-27target/riscv: Rename the H irqs to VS irqsAlistair Francis
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis
2020-02-27target/riscv: Convert MIP CSR to target_ulongAlistair Francis
2020-01-24qdev: set properties with device_class_set_props()Marc-André Lureau
2020-01-24cpu: Use cpu_class_set_parent_reset()Greg Kurz
2019-11-14target/riscv: Remove atomic accesses to MIP CSRAlistair Francis
2019-10-28RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt
2019-09-17target/riscv: Use both register name and ABI nameAtish Patra
2019-08-19target/riscv: rationalise softfloat includesAlex Bennée
2019-06-25RISC-V: Clear load reservations on context switch and SCJoel Sing
2019-06-25RISC-V: Add support for the Zicsr extensionPalmer Dabbelt
2019-06-25RISC-V: Add support for the Zifencei extensionPalmer Dabbelt
2019-06-25target/riscv: Add support for disabling/enabling CountersAlistair Francis
2019-06-25target/riscv: Remove user version informationAlistair Francis
2019-06-25target/riscv: Require either I or E base extensionAlistair Francis
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