slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2021-12-20	target/riscv: gdb: support vector registers for rv64 & rv32	Hsiangkai Wang
2021-12-20	target/riscv: drop vector 0.7.1 and add 1.0 support	Frank Chang
2021-12-20	target/riscv: zfh: add Zfhmin cpu property	Frank Chang
2021-12-20	target/riscv: zfh: add Zfh cpu property	Frank Chang
2021-11-02	target/riscv: Make riscv_cpu_tlb_fill sysemu only	Richard Henderson
2021-10-28	target/riscv: Allow experimental J-ext to be turned on	Alexey Baturo
2021-10-28	target/riscv: Print new PM CSRs in QEMU logs	Alexey Baturo
2021-10-28	target/riscv: Support CSRs required for RISC-V PM extension except for the h-...	Alexey Baturo
2021-10-22	target/riscv: Use riscv_csrrw_debug for cpu_dump	Richard Henderson
2021-10-22	target/riscv: Add MXL/SXL/UXL to TB_FLAGS	Richard Henderson
2021-10-22	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	Richard Henderson
2021-10-22	target/riscv: Split misa.mxl and misa.ext	Richard Henderson
2021-10-22	target/riscv: Organise the CPU properties	Alistair Francis
2021-10-22	target/riscv: line up all of the registers in the info register dump	Travis Geiselbrecht
2021-10-07	target/riscv: Remove RVB (replaced by Zb[abcs])	Philipp Tomsich
2021-10-07	target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties	Philipp Tomsich
2021-09-21	target/riscv: Expose interrupt pending bits as GPIO lines	Alistair Francis
2021-09-21	target/riscv: Update the ePMP CSR address	Alistair Francis
2021-09-14	target/riscv: Restrict cpu_exec_interrupt() handler to sysemu	Philippe Mathieu-Daudé
2021-09-01	target/riscv: Don't wrongly override isa version	LIU Zhiwei
2021-06-08	target/riscv: rvb: add b-ext version cpu option	Frank Chang
2021-06-08	target/riscv: rvb: support and turn on B-extension from command line	Kito Cheng
2021-06-08	target/riscv: Dump CSR mscratch/sscratch/satp	Changbin Du
2021-06-08	target/riscv: Remove unnecessary riscv_*_names[] declaration	Bin Meng
2021-05-26	hw/core: Constify TCGCPUOps	Richard Henderson
2021-05-26	cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps	Philippe Mathieu-Daudé
2021-05-26	cpu: Move CPUClass::write_elf* to SysemuCPUOps	Philippe Mathieu-Daudé
2021-05-26	cpu: Move CPUClass::vmsd to SysemuCPUOps	Philippe Mathieu-Daudé
2021-05-26	cpu: Introduce SysemuCPUOps structure	Philippe Mathieu-Daudé
2021-05-26	cpu: Rename CPUClass vmsd -> legacy_vmsd	Philippe Mathieu-Daudé
2021-05-11	target/riscv: Remove the hardcoded RVXLEN macro	Alistair Francis
2021-05-11	target/riscv: fix a typo with interrupt names	Emmanuel Blot
2021-05-11	target/riscv: Add ePMP support for the Ibex CPU	Alistair Francis
2021-05-11	target/riscv: Add a config option for ePMP	Hou Weiying
2021-05-11	target/riscv: Convert the RISC-V exceptions to an enum	Alistair Francis
2021-05-11	target/riscv: Add Shakti C class CPU	Vijai Kumar K
2021-05-11	target/riscv: Align the data type of reset vector address	Dylan Jhong
2021-05-11	target/riscv: Remove privilege v1.9 specific CSR related code	Atish Patra
2021-03-22	target/riscv: Add proper two-stage lookup exception detection	Georg Kotheimer
2021-03-09	Various spelling fixes	Michael Tokarev
2021-03-04	target-riscv: support QMP dump-guest-memory	Yifei Jiang
2021-02-05	cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass	Claudio Fontana
2021-02-05	cpu: move do_unaligned_access to tcg_ops	Claudio Fontana
2021-02-05	cpu: move cc->transaction_failed to tcg_ops	Claudio Fontana
2021-02-05	cpu: move cc->do_interrupt to tcg_ops	Claudio Fontana
2021-02-05	cpu: Move tlb_fill to tcg_ops	Eduardo Habkost
2021-02-05	cpu: Move cpu_exec_* to tcg_ops	Eduardo Habkost
2021-02-05	cpu: Move synchronize_from_tb() to tcg_ops	Eduardo Habkost
2021-02-05	target/riscv: remove CONFIG_TCG, as it is always TCG	Claudio Fontana
2021-02-05	cpu: Introduce TCGCpuOperations struct	Eduardo Habkost