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path: root/target/riscv/cpu.c
AgeCommit message (Expand)Author
2022-02-16target/riscv: add support for svpbmt extensionWeiwei Li
2022-02-16target/riscv: add support for svinval extensionWeiwei Li
2022-02-16target/riscv: add support for svnapot extensionWeiwei Li
2022-02-16target/riscv: Allow users to force enable AIA CSRs in HARTAnup Patel
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel
2022-02-16target/riscv: Allow setting CPU feature from machine/device emulationAnup Patel
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel
2022-02-16target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel
2022-02-16target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich
2022-02-16target/riscv: correct "code should not be reached" for x-rv128Frédéric Pétrot
2022-01-21target/riscv: Set default XLEN for hypervisorLIU Zhiwei
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei
2022-01-21target/riscv: Use gdb xml according to max mxlenLIU Zhiwei
2022-01-21target/riscv: Extend pc for runtime pc writeLIU Zhiwei
2022-01-21target/riscv: Create xl field in envLIU Zhiwei
2022-01-21target/riscv: rvv-1.0: Allow Zve32f extension to be turned onFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang
2022-01-21target/riscv: rvv-1.0: Allow Zve64f extension to be turned onFrank Chang
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang
2022-01-21target/riscv: Add host cpu typeYifei Jiang
2022-01-21target/riscv: Support setting external interrupt by KVMYifei Jiang
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot
2022-01-08target/riscv: Fix position of 'experimental' commentPhilipp Tomsich
2022-01-08target/riscv: Enable the Hypervisor extension by defaultAlistair Francis
2022-01-08target/riscv: Mark the Hypervisor extension as non experimentalAlistair Francis
2021-12-20target/riscv: Enable bitmanip Zb[abcs] instructionsVineet Gupta
2021-12-20target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang
2021-12-20target/riscv: drop vector 0.7.1 and add 1.0 supportFrank Chang
2021-12-20target/riscv: zfh: add Zfhmin cpu propertyFrank Chang
2021-12-20target/riscv: zfh: add Zfh cpu propertyFrank Chang
2021-11-02target/riscv: Make riscv_cpu_tlb_fill sysemu onlyRichard Henderson
2021-10-28target/riscv: Allow experimental J-ext to be turned onAlexey Baturo
2021-10-28target/riscv: Print new PM CSRs in QEMU logsAlexey Baturo
2021-10-28target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo
2021-10-22target/riscv: Use riscv_csrrw_debug for cpu_dumpRichard Henderson
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson
2021-10-22target/riscv: Split misa.mxl and misa.extRichard Henderson
2021-10-22target/riscv: Organise the CPU propertiesAlistair Francis
2021-10-22target/riscv: line up all of the registers in the info register dumpTravis Geiselbrecht
2021-10-07target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich
2021-10-07target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich
2021-09-21target/riscv: Expose interrupt pending bits as GPIO linesAlistair Francis
2021-09-21target/riscv: Update the ePMP CSR addressAlistair Francis
2021-09-14target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé
2021-09-01target/riscv: Don't wrongly override isa versionLIU Zhiwei
2021-06-08target/riscv: rvb: add b-ext version cpu optionFrank Chang
2021-06-08target/riscv: rvb: support and turn on B-extension from command lineKito Cheng
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