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path: root/target/riscv/cpu.c
AgeCommit message (Expand)Author
2023-10-12target/riscv/cpu.c: limit cfg->vext_spec log messageDaniel Henrique Barboza
2023-10-12target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()Daniel Henrique Barboza
2023-10-12target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()Daniel Henrique Barboza
2023-10-12target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]Daniel Henrique Barboza
2023-10-12target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]Daniel Henrique Barboza
2023-10-12target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]Daniel Henrique Barboza
2023-10-12target/riscv/cpu.c: split kvm prop handling to its own helperDaniel Henrique Barboza
2023-10-12target/riscv/cpu.c: skip 'bool' check when filtering KVM propsDaniel Henrique Barboza
2023-10-12target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]Daniel Henrique Barboza
2023-10-11hw/core/cpu: Return static value with gdb_arch_name()Akihiko Odaki
2023-10-04accel/tcg: Remove cpu_set_cpustate_pointersRichard Henderson
2023-10-03target/*: Add instance_align to all cpu base classesRichard Henderson
2023-09-29target/riscv: cpu: Fixup local variables shadowingAlistair Francis
2023-09-11target/riscv: Allocate itrigger timers only onceAkihiko Odaki
2023-09-11riscv: zicond: make non-experimentalVineet Gupta
2023-09-11target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0Daniel Henrique Barboza
2023-09-11target/riscv: Update CSR bits name for svadu extensionWeiwei Li
2023-09-11target/riscv: Add Zihintntl extension ISA string to DTSJason Chien
2023-09-11target/riscv: Add Zvksed ISA extension supportMax Chou
2023-09-11target/riscv: Add Zvkg ISA extension supportNazar Kazakov
2023-09-11target/riscv: Add Zvksh ISA extension supportLawrence Hunter
2023-09-11target/riscv: Add Zvknh ISA extension supportKiran Ostrolenk
2023-09-11target/riscv: Add Zvkned ISA extension supportNazar Kazakov
2023-09-11target/riscv: Add Zvbb ISA extension supportDickon Hood
2023-09-11target/riscv: Add Zvbc ISA extension supportLawrence Hunter
2023-09-11target/riscv/cpu.c: add smepmp isa stringDaniel Henrique Barboza
2023-09-11target/riscv/cpu.c: add zmmul isa stringDaniel Henrique Barboza
2023-09-11target/riscv/cpu.c: do not run 'host' CPU with TCGDaniel Henrique Barboza
2023-07-19target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcfDaniel Henrique Barboza
2023-07-10riscv: Add support for the Zfa extensionChristoph Müllner
2023-07-10target/riscv/cpu.c: create KVM mock propertiesDaniel Henrique Barboza
2023-07-10target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext()Daniel Henrique Barboza
2023-07-10target/riscv/cpu.c: add satp_mode properties earlierDaniel Henrique Barboza
2023-07-10target/riscv/kvm.c: add multi-letter extension KVM propertiesDaniel Henrique Barboza
2023-07-10target/riscv: add KVM specific MISA propertiesDaniel Henrique Barboza
2023-07-10target/riscv/cpu: add misa_ext_info_arr[]Daniel Henrique Barboza
2023-07-10target/riscv: use KVM scratch CPUs to init KVM propertiesDaniel Henrique Barboza
2023-07-10target/riscv/cpu.c: restrict 'marchid' valueDaniel Henrique Barboza
2023-07-10target/riscv/cpu.c: restrict 'mimpid' valueDaniel Henrique Barboza
2023-07-10target/riscv/cpu.c: restrict 'mvendorid' valueDaniel Henrique Barboza
2023-07-10target/riscv: skip features setup for KVM CPUsDaniel Henrique Barboza
2023-07-10target/riscv: Expose properties for BF16 extensionsWeiwei Li
2023-07-10target/riscv: Add properties for BF16 extensionsWeiwei Li
2023-07-10target/riscv: Add RVV registers to logIvan Klokov
2023-07-10target/riscv/cpu.c: fix veyron-v1 CPU propertiesDaniel Henrique Barboza
2023-07-10target/riscv: Use xl instead of mxl for disassembleLIU Zhiwei
2023-06-28target/riscv: Restrict KVM-specific fields from ArchCPUPhilippe Mathieu-Daudé
2023-06-13target/riscv: Enable PC-relative translationWeiwei Li
2023-06-13target/riscv: Pass RISCVCPUConfig as target_info to disassemble_infoWeiwei Li
2023-06-13target/riscv: smstateen knobsMayuresh Chitale
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