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path: root/target/riscv/cpu.c
AgeCommit message (Expand)Author
2023-03-03Merge tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt...Peter Maydell
2023-03-01Merge patch series "target/riscv: Add support for Svadu extension"Palmer Dabbelt
2023-03-01target/riscv: Export Svadu propertyWeiwei Li
2023-03-01target/riscv: Add *envcfg.HADE related check in address translationWeiwei Li
2023-03-01target/riscv: Add *envcfg.PBMTE related check in address translationWeiwei Li
2023-03-01target/riscv: Add support for Zicond extensionWeiwei Li
2023-03-01Merge patch series "target/riscv: Some updates to float point related extensi...Palmer Dabbelt
2023-03-01target/riscv: Expose properties for Zv* extensionsWeiwei Li
2023-03-01target/riscv: Indent fixes in cpu.cWeiwei Li
2023-03-01target/riscv: Add property check for Zvfh{min} extensionsWeiwei Li
2023-03-01target/riscv: Fix relationship between V, Zve*, F and DWeiwei Li
2023-03-01target/riscv: Fix the relationship between Zhinxmin and ZhinxWeiwei Li
2023-03-01target/riscv: Fix the relationship between Zfhmin and ZfhWeiwei Li
2023-03-01target/riscv: remove RISCV_FEATURE_MMUDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_EPMPDaniel Henrique Barboza
2023-03-01target/riscv/cpu.c: error out if EPMP is enabled without PMPDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_DEBUGDaniel Henrique Barboza
2023-03-01target/riscv: allow MISA writes as experimentalDaniel Henrique Barboza
2023-03-01target/riscv: Replace `tb_pc()` with `tb->pc`Anton Johansson
2023-02-23target/riscv: Remove privileged spec version restriction for RVVFrank Chang
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner
2023-02-07RISC-V: Add initial support for T-Head C906Christoph Müllner
2023-02-07RISC-V: Set minimum priv version for Zfh to 1.11Christoph Müllner
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBa ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner
2023-01-20target/riscv: Use TARGET_FMT_lx for env->mhartidBin Meng
2023-01-20target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()Daniel Henrique Barboza
2023-01-20target/riscv/cpu: set cpu->cfg in register_cpu_props()Daniel Henrique Barboza
2023-01-20target/riscv/cpu.c: Fix elen checkDongxue Zhang
2023-01-06RISC-V: Add Zawrs ISA extension supportChristoph Muellner
2023-01-06target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()Bin Meng
2022-12-16target/riscv: Convert to 3-phase resetPeter Maydell
2022-10-26target/riscv: Convert to tcg_ops restore_state_to_opcRichard Henderson
2022-10-04accel/tcg: Introduce tb_pc and log_pcRichard Henderson
2022-10-04hw/core: Add CPUClass.get_pcRichard Henderson
2022-09-27target/riscv: Set the CPU resetvec directlyAlistair Francis
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra
2022-09-07target/riscv: Add stimecmp supportAtish Patra
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel
2022-09-07target/riscv: Add xicondops in ISA entryRahul Pathak
2022-09-07target/riscv: Add Zihintpause supportDao Lu
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