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2023-06-13target/riscv: rework write_misa()Daniel Henrique Barboza
write_misa() must use as much common logic as possible. We want to open code just the bits that are exclusive to the CSR write operation and TCG internals. Our validation is done with riscv_cpu_validate_set_extensions(), but we need a small tweak first. When enabling RVG we're doing: env->misa_ext |= RVI | RVM | RVA | RVF | RVD; env->misa_ext_mask = env->misa_ext; This works fine for realize() time but this can potentially overwrite env->misa_ext_mask if we reutilize the function for write_misa(). Instead of doing misa_ext_mask = misa_ext, sum up the RVG extensions in misa_ext_mask as well. This won't change realize() time behavior (misa_ext_mask will be == misa_ext) and will ensure that write_misa() won't change misa_ext_mask by accident. After that, rewrite write_misa() to work as follows: - mask the write using misa_ext_mask to avoid enabling unsupported extensions; - suppress RVC if the next insn isn't aligned; - disable RVG if any of RVG dependencies are being disabled by the user; - assign env->misa_ext and run riscv_cpu_validate_set_extensions(). On error, rollback env->misa_ext to its original value, logging a GUEST_ERROR to inform the user about the failed write; - handle RVF and MSTATUS_FS and continue as usual. Let's keep write_misa() as experimental for now until this logic gains enough mileage. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230517135714.211809-12-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()Daniel Henrique Barboza
We have 4 config settings being done in riscv_cpu_init(): ext_ifencei, ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu" device, which happens to be the parent device of every RISC-V cpu. The result is that these 4 configs are being set every time, and every other CPU should always account for them. CPUs such as sifive_e need to disable settings that aren't enabled simply because the parent class happens to be enabling it. Moving all configurations from the parent class to each CPU will centralize the config of each CPU into its own init(), which is clearer than having to account to whatever happens to be set in the parent device. These settings are also being set in register_cpu_props() when no 'misa_ext' is set, so for these CPUs we don't need changes. Named CPUs will receive all cfgs that the parent were setting into their init(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-11-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/cpu.c: validate extensions before riscv_timer_init()Daniel Henrique Barboza
There is no need to init timers if we're not even sure that our extensions are valid. Execute riscv_cpu_validate_set_extensions() before riscv_timer_init(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()Daniel Henrique Barboza
Let's remove more code that is open coded in riscv_cpu_realize() and put it into a helper. Let's also add an error message instead of just asserting out if env->misa_mxl_max != env->misa_mlx. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/cpu.c: add priv_spec validate/disable_exts helpersDaniel Henrique Barboza
We're doing env->priv_spec validation and assignment at the start of riscv_cpu_realize(), which is fine, but then we're doing a force disable on extensions that aren't compatible with the priv version. This second step is being done too early. The disabled extensions might be re-enabled again in riscv_cpu_validate_set_extensions() by accident. A better place to put this code is at the end of riscv_cpu_validate_set_extensions() after all the validations are completed. Add a new helper, riscv_cpu_disable_priv_spec_isa_exts(), to disable the extesions after the validation is done. While we're at it, create a riscv_cpu_validate_priv_spec() helper to host all env->priv_spec related validation to unclog riscv_cpu_realize a bit. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Mask the implicitly enabled extensions in isa_string based on ↵Weiwei Li
priv version Using implicitly enabled extensions such as Zca/Zcf/Zcd instead of their super extensions can simplify the extension related check. However, they may have higher priv version than their super extensions. So we should mask them in the isa_string based on priv version to make them invisible to user if the specified priv version is lower than their minimal priv version. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: add PRIV_VERSION_LATESTDaniel Henrique Barboza
All these generic CPUs are using the latest priv available, at this moment PRIV_VERSION_1_12_0: - riscv_any_cpu_init() - rv32_base_cpu_init() - rv64_base_cpu_init() - rv128_base_cpu_init() Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll make it easier to update everything at once when a new priv version is available. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/cpu.c: remove set_priv_version()Daniel Henrique Barboza
The setter is doing nothing special. Just set env->priv_ver directly. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/cpu.c: remove set_vext_version()Daniel Henrique Barboza
This setter is doing nothing else but setting env->vext_ver. Assign the value directly. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/cpu.c: add riscv_cpu_validate_v()Daniel Henrique Barboza
The RVV verification will error out if fails and it's being done at the end of riscv_cpu_validate_set_extensions(), after we've already set some extensions that are dependent on RVV. Let's put it in its own function and do it earlier. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Move zc* out of the experimental propertiesWeiwei Li
Zc* extensions (version 1.0) are ratified. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20230510030040.20528-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add Ventana's Veyron V1 CPURahul Pathak
Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs exclusively for the rv64 target. It's tested with the 'virt' board. CPU specs and general information can be found here: https://www.nextplatform.com/2023/02/02/the-first-risc-v-shot-across-the-datacenter-bow/ Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230418123624.16414-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add TYPE_RISCV_DYNAMIC_CPUDaniel Henrique Barboza
This new abstract type will be used to differentiate between static and non-static CPUs in query-cpu-definitions. All generic CPUs were changed to be of this type. Named CPUs are kept as TYPE_RISCV_CPU and will still be considered static. This is the output of query-cpu-definitions after this change for the riscv64 target: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio {"QMP": {"version": (...)} {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}} {"return": {}} {"execute": "query-cpu-definitions"} {"return": [ {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": false}, {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": true, "deprecated": false}, {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": false}, {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "deprecated": false}, {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": true, "deprecated": false}, {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": true, "deprecated": false}, {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": true, "deprecated": false} ]} Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230411183511.189632-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Add a general status enum for extensionsLIU Zhiwei
The pointer masking is the only extension that directly use status. The vector or float extension uses the status in an indirect way. Replace the pointer masking extension special status fields with the general status. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20230324143031.1093-3-zhiwei_liu@linux.alibaba.com> [rth: Add a typedef for the enum] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-3-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-3-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Use check for relationship between Zdinx/Zhinx{min} and ZfinxWeiwei Li
Zdinx/Zhinx{min} require Zfinx. And require relationship is usually done by check currently. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230408135908.25269-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv/cpu.c: redesign register_cpu_props()Daniel Henrique Barboza
The function is now a no-op for all cpu_init() callers that are setting a non-zero misa value in set_misa(), since it's no longer used to sync cpu->cfg props with env->misa_ext bits. Remove it in those cases. While we're at it, rename the function to match what it's actually doing: create user properties to set/remove CPU extensions. Make a note that it will overwrite env->misa_ext with the defaults set by each user property. Update the MISA bits comment in cpu.h as well. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-21-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add RVG and remove cpu->cfg.ext_gDaniel Henrique Barboza
We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it the same way we did with the others: create a "g" RISCVCPUMisaExtConfig property, remove the old "g" property, remove all instances of 'cfg.ext_g' and use riscv_has_ext(env, RVG). The caveat is that we don't have RVG, so add it. RVG will be used right off the bat in set_misa() of rv64_thead_c906_cpu_init() because the CPU is enabling G via the now removed 'ext_g' flag. After this patch, there are no more MISA extensions represented by flags in RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-20-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()Daniel Henrique Barboza
This CPU is enabling G via cfg.ext_g and, at the same time, setting IMAFD in set_misa() and cfg.ext_icsr. riscv_cpu_validate_set_extensions() is already doing that, so there's no need for cpu_init() setups to worry about setting G and its extensions. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-19-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove riscv_cpu_sync_misa_cfg()Daniel Henrique Barboza
This function was created to move the sync between cpu->cfg.ext_N bit changes to env->misa_ext* from the validation step to an ealier step, giving us a guarantee that we could use either cpu->cfg.ext_N or riscv_has_ext(env,N) in the validation. We don't have any cpu->cfg.ext_N left that has an existing MISA bit (cfg.ext_g will be handled shortly). The function is now a no-op, simply copying the existing values of misa_ext* back to misa_ext*. Remove it. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-18-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove cpu->cfg.ext_vDaniel Henrique Barboza
Create a new "v" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are replaced with riscv_has_ext(env, RVV). Remove the old "v" property and 'ext_v' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-17-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove cpu->cfg.ext_jDaniel Henrique Barboza
Create a new "j" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are replaced with riscv_has_ext(env, RVJ). Remove the old "j" property and 'ext_j' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-16-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove cpu->cfg.ext_hDaniel Henrique Barboza
Create a new "h" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVH. Instances of cpu->cfg.ext_h and similar are replaced with riscv_has_ext(env, RVH). Remove the old "h" property and 'ext_h' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-15-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove cpu->cfg.ext_uDaniel Henrique Barboza
Create a new "u" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are replaced with riscv_has_ext(env, RVU). Remove the old "u" property and 'ext_u' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-14-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove cpu->cfg.ext_sDaniel Henrique Barboza
Create a new "s" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are replaced with riscv_has_ext(env, RVS). Remove the old "s" property and 'ext_s' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-13-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove cpu->cfg.ext_mDaniel Henrique Barboza
Create a new "m" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are replaced with riscv_has_ext(env, RVM). Remove the old "m" property and 'ext_m' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-12-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove cpu->cfg.ext_eDaniel Henrique Barboza
Create a new "e" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are replaced with riscv_has_ext(env, RVE). Remove the old "e" property and 'ext_e' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-11-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove cpu->cfg.ext_iDaniel Henrique Barboza
Create a new "i" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are replaced with riscv_has_ext(env, RVI). Remove the old "i" property and 'ext_i' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove cpu->cfg.ext_fDaniel Henrique Barboza
Create a new "f" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVF. Instances of cpu->cfg.ext_f and similar are replaced with riscv_has_ext(env, RVF). Remove the old "f" property and 'ext_f' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove cpu->cfg.ext_dDaniel Henrique Barboza
Create a new "d" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are replaced with riscv_has_ext(env, RVD). Remove the old "d" property and 'ext_d' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove cpu->cfg.ext_cDaniel Henrique Barboza
Create a new "c" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are replaced with riscv_has_ext(env, RVC). Remove the old "c" property and 'ext_c' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove cpu->cfg.ext_aDaniel Henrique Barboza
Create a new "a" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are replaced with riscv_has_ext(env, RVA). Remove the old "a" property and 'ext_a' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: introduce riscv_cpu_add_misa_properties()Daniel Henrique Barboza
Ever since RISCVCPUConfig got introduced users are able to set CPU extensions in the command line. User settings are reflected in the cpu->cfg object for later use. These properties are used in the target/riscv/cpu.c code, most notably in riscv_cpu_validate_set_extensions(), where most of our realize time validations are made. And then there's env->misa_ext, the field where the MISA extensions are set, that is read everywhere else. We need to keep env->misa_ext updated with cpu->cfg settings, since our validations rely on it, forcing us to make register_cpu_props() write cpu->cfg.ext_N flags to cover for named CPUs that aren't used named properties but also needs to go through the same validation steps. Failing to so will make those name CPUs fail validation (see c66ffcd5358b for more info). Not only that, but we also need to sync env->misa_ext with cpu->cfg again during realize() time to catch any change the user might have done, since the rest of the code relies on that. Making cpu->cfg.ext_N and env->misa_ext reflect each other is not needed. What we want is a way for users to enable/disable MISA extensions, and there's nothing stopping us from letting the user write env->misa_ext directly. Here are the artifacts that will enable us to do that: - RISCVCPUMisaExtConfig will declare each MISA property; - cpu_set_misa_ext_cfg() is the setter for each property. We'll write env->misa_ext and env->misa_ext_mask with the appropriate misa_bit; cutting off cpu->cfg.ext_N from the logic; - cpu_get_misa_ext_cfg() is a getter that will retrieve the current val of the property based on env->misa_ext; - riscv_cpu_add_misa_properties() will be called in register_cpu_props() to init all MISA properties from the misa_ext_cfgs[] array. With this infrastructure we'll start to get rid of each cpu->cfg.ext_N attribute in the next patches. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv/cpu.c: remove 'multi_letter' from isa_ext_dataDaniel Henrique Barboza
We don't have MISA extensions in isa_edata_arr[] anymore. Remove the redundant 'multi_letter' field from isa_ext_data. Suggested-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: remove MISA properties from isa_edata_arr[]Daniel Henrique Barboza
The code that disables extensions if there's a priv version mismatch uses cpu->cfg.ext_N properties to do its job. We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split the MISA related verifications in a new function, removing it from isa_edata_arr[]. We're also erroring it out instead of disabling, making the cpu_init() function responsible for running an adequate priv spec for the MISA extensions it wants to use. Note that the RVV verification is being ignored since we're always have at least PRIV_VERSION_1_10_0. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: sync env->misa_ext* with cpu->cfg in realize()Daniel Henrique Barboza
When riscv_cpu_realize() starts we're guaranteed to have cpu->cfg.ext_N properties updated. The same can't be said about env->misa_ext*, since the user might enable/disable MISA extensions in the command line, and env->misa_ext* won't caught these changes. The current solution is to sync everything at the end of validate_set_extensions(), checking every cpu->cfg.ext_N value to do a set_misa() in the end. The last change we're making in the MISA cfg flags are in the G extension logic, enabling IMAFG if cpu->cfg_ext.g is enabled. Otherwise we're not making any changes in MISA bits ever since realize() starts. There's no reason to postpone misa_ext updates until the end of the validation. Let's do it earlier, during realize(), in a new helper called riscv_cpu_sync_misa_cfg(). If cpu->cfg.ext_g is enabled, do it again by updating env->misa_ext* directly. This is a pre-requisite to allow riscv_cpu_validate_set_extensions() to use riscv_has_ext() instead of cpu->cfg.ext_N to validate the MISA extensions, which is our end goal here. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li
Fix lines with over 80 characters for both code and comments. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230405085813.40643-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Fix format for commentsWeiwei Li
Fix formats for multi-lines comments. Add spaces around single line comments(after "/*" and before "*/"). Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230405085813.40643-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Fix format for indentationWeiwei Li
Fix identation problems, and try to use the same indentation strategy in the same file. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230405085813.40643-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li
Directly use env->virt_enabled instead. Suggested-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230405085813.40643-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Add support for ZceWeiwei Li
Add and expose property for Zce: * Specifying Zce without F includes Zca, Zcb, Zcmp, Zcmt. * Specifying Zce with F includes Zca, Zcb, Zcmp, Zcmt and Zcf. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-11-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: expose properties for Zc* extensionWeiwei Li
Expose zca,zcb,zcf,zcd,zcmp,zcmt properties. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-9-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add cfg properties for Zc* extensionWeiwei Li
Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension. Add check for these properties. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li
Use CPURISCVState as argument directly in riscv_cpu_update_mip and riscv_timer_write_timecmp, since type converts from CPURISCVState to RISCVCPU in many caller of them and then back to CPURISCVState in them. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230309071329.45932-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Fix priv version dependency for vector and zfhLIU Zhiwei
Vector implicitly enables zve64d, zve64f, zve32f sub extensions. As vector only requires PRIV_1_10_0, these sub extensions should not require priv version higher than that. The same for Zfh. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20230321043415.754-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-03-06riscv: Introduce satp mode hw capabilitiesAlexandre Ghiti
Currently, the max satp mode is set with the only constraint that it must be implemented in QEMU, i.e. set in valid_vm_1_10_[32|64]. But we actually need to add another level of constraint: what the hw is actually capable of, because currently, a linux booting on a sifive-u54 boots in sv57 mode which is incompatible with the cpu's sv39 max capability. So add a new bitmap to RISCVSATPMap which contains this capability and initialize it in every XXX_cpu_init. Finally: - valid_vm_1_10_[32|64] constrains which satp mode the CPU can use - the CPU hw capabilities constrains what the user may select - the user's selection then constrains what's available to the guest OS. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230303131252.892893-5-alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06riscv: Allow user to set the satp modeAlexandre Ghiti
RISC-V specifies multiple sizes for addressable memory and Linux probes for the machine's support at startup via the satp CSR register (done in csr.c:validate_vm). As per the specification, sv64 must support sv57, which in turn must support sv48...etc. So we can restrict machine support by simply setting the "highest" supported mode and the bare mode is always supported. You can set the satp mode using the new properties "sv32", "sv39", "sv48", "sv57" and "sv64" as follows: -cpu rv64,sv57=on # Linux will boot using sv57 scheme -cpu rv64,sv39=on # Linux will boot using sv39 scheme -cpu rv64,sv57=off # Linux will boot using sv48 scheme -cpu rv64 # Linux will boot using sv57 scheme by default We take the highest level set by the user: -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme We make sure that invalid configurations are rejected: -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are # enabled We accept "redundant" configurations: -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme And contradictory configurations: -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme Co-Developed-by: Ludovic Henry <ludovic@rivosinc.com> Signed-off-by: Ludovic Henry <ludovic@rivosinc.com> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-ID: <20230303131252.892893-4-alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06riscv: Pass Object to register_cpu_props instead of DeviceStateAlexandre Ghiti
One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Message-ID: <20230303131252.892893-2-alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05target/riscv: cpu: Implement get_arch_id callbackMayuresh Chitale
Implement the callback for getting the architecture-dependent CPU ID ie mhartid. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230303065055.915652-2-mchitale@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05target/riscv: implement Zicbom extensionChristoph Muellner
Zicbom is the Cache-Block Management extension defined in the already ratified RISC-V Base Cache Management Operation (CBO) ISA extension [1]. The extension contains three instructions: cbo.clean, cbo.flush and cbo.inval. All of them must be implemented in the same group as LQ and cbo.zero due to overlapping patterns. All these instructions can throw a Illegal Instruction/Virtual Instruction exception, similar to the existing cbo.zero. The same check_zicbo_envcfg() is used to handle these exceptions. Aside from that, these instructions also need to handle page faults and guest page faults. This is done in a new check_zicbom_access() helper. As with Zicboz, the cache block size for Zicbom is also configurable. Note that the spec determines that Zicbo[mp] and Zicboz can have different cache sizes (Section 2.7 of [1]), so we also include a 'cbom_blocksize' to go along with the existing 'cboz_blocksize'. They are set to the same size, so unless users want to play around with the settings both sizes will be the same. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230224132536.552293-4-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner
The RISC-V base cache management operation (CBO) ISA extension has been ratified. It defines three extensions: Cache-Block Management, Cache-Block Prefetch and Cache-Block Zero. More information about the spec can be found at [1]. Let's start by implementing the Cache-Block Zero extension, Zicboz. It uses the cbo.zero instruction that, as with all CBO instructions that will be added later, needs to be implemented in an overlap group with the LQ instruction due to overlapping patterns. cbo.zero throws a Illegal Instruction/Virtual Instruction exception depending on CSR state. This is also the case for the remaining cbo instructions we're going to add next, so create a check_zicbo_envcfg() that will be used by all Zicbo[mz] instructions. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230224132536.552293-3-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-18 04:17:33 +0000