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path: root/target/riscv/cpu.c
AgeCommit message (Expand)Author
2023-05-05target/riscv: add Ventana's Veyron V1 CPURahul Pathak
2023-05-05target/riscv: add TYPE_RISCV_DYNAMIC_CPUDaniel Henrique Barboza
2023-05-05target/riscv: Add a general status enum for extensionsLIU Zhiwei
2023-05-05target/riscv: Use check for relationship between Zdinx/Zhinx{min} and ZfinxWeiwei Li
2023-05-05target/riscv/cpu.c: redesign register_cpu_props()Daniel Henrique Barboza
2023-05-05target/riscv: add RVG and remove cpu->cfg.ext_gDaniel Henrique Barboza
2023-05-05target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()Daniel Henrique Barboza
2023-05-05target/riscv: remove riscv_cpu_sync_misa_cfg()Daniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_vDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_jDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_hDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_uDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_sDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_mDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_eDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_iDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_fDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_dDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_cDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_aDaniel Henrique Barboza
2023-05-05target/riscv: introduce riscv_cpu_add_misa_properties()Daniel Henrique Barboza
2023-05-05target/riscv/cpu.c: remove 'multi_letter' from isa_ext_dataDaniel Henrique Barboza
2023-05-05target/riscv: remove MISA properties from isa_edata_arr[]Daniel Henrique Barboza
2023-05-05target/riscv: sync env->misa_ext* with cpu->cfg in realize()Daniel Henrique Barboza
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li
2023-05-05target/riscv: Fix format for commentsWeiwei Li
2023-05-05target/riscv: Fix format for indentationWeiwei Li
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li
2023-05-05target/riscv: Add support for ZceWeiwei Li
2023-05-05target/riscv: expose properties for Zc* extensionWeiwei Li
2023-05-05target/riscv: add cfg properties for Zc* extensionWeiwei Li
2023-05-05target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li
2023-05-05target/riscv: Fix priv version dependency for vector and zfhLIU Zhiwei
2023-03-06riscv: Introduce satp mode hw capabilitiesAlexandre Ghiti
2023-03-06riscv: Allow user to set the satp modeAlexandre Ghiti
2023-03-06riscv: Pass Object to register_cpu_props instead of DeviceStateAlexandre Ghiti
2023-03-05target/riscv: cpu: Implement get_arch_id callbackMayuresh Chitale
2023-03-05target/riscv: implement Zicbom extensionChristoph Muellner
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner
2023-03-03Merge tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt...Peter Maydell
2023-03-01Merge patch series "target/riscv: Add support for Svadu extension"Palmer Dabbelt
2023-03-01target/riscv: Export Svadu propertyWeiwei Li
2023-03-01target/riscv: Add *envcfg.HADE related check in address translationWeiwei Li
2023-03-01target/riscv: Add *envcfg.PBMTE related check in address translationWeiwei Li
2023-03-01target/riscv: Add support for Zicond extensionWeiwei Li
2023-03-01Merge patch series "target/riscv: Some updates to float point related extensi...Palmer Dabbelt
2023-03-01target/riscv: Expose properties for Zv* extensionsWeiwei Li
2023-03-01target/riscv: Indent fixes in cpu.cWeiwei Li
2023-03-01target/riscv: Add property check for Zvfh{min} extensionsWeiwei Li
2023-03-01target/riscv: Fix relationship between V, Zve*, F and DWeiwei Li
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