slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2020-06-08	Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-re...	Peter Maydell
2020-06-05	target/riscv/cpu: Restrict CPU migration to system-mode	Philippe Mathieu-Daudé
2020-06-03	target/riscv: Add the lowRISC Ibex CPU	Alistair Francis
2020-06-03	target/riscv: Don't set PMP feature in the cpu init	Alistair Francis
2020-06-03	target/riscv: Disable the MMU correctly	Alistair Francis
2020-06-03	target/riscv: Don't overwrite the reset vector	Alistair Francis
2020-06-03	target/riscv: Drop support for ISA spec version 1.09.1	Alistair Francis
2020-06-03	target/riscv: Remove the deprecated CPUs	Alistair Francis
2020-04-29	target/riscv: Add a sifive-e34 cpu type	Corey Wharton
2020-03-17	cpu: Use DeviceClass reset instead of a special CPUClass reset	Peter Maydell
2020-03-05	RISC-V: Add a missing "," in riscv_excp_names	Palmer Dabbelt
2020-02-27	target/riscv: Allow enabling the Hypervisor extension	Alistair Francis
2020-02-27	target/riscv: Add support for the 32-bit MSTATUSH CSR	Alistair Francis
2020-02-27	target/riscv: Dump Hypervisor registers if enabled	Alistair Francis
2020-02-27	target/riscv: Rename the H irqs to VS irqs	Alistair Francis
2020-02-27	target/riscv: Add support for the new execption numbers	Alistair Francis
2020-02-27	target/riscv: Convert MIP CSR to target_ulong	Alistair Francis
2020-01-24	qdev: set properties with device_class_set_props()	Marc-André Lureau
2020-01-24	cpu: Use cpu_class_set_parent_reset()	Greg Kurz
2019-11-14	target/riscv: Remove atomic accesses to MIP CSR	Alistair Francis
2019-10-28	RISC-V: Implement cpu_do_transaction_failed	Palmer Dabbelt
2019-09-17	target/riscv: Use both register name and ABI name	Atish Patra
2019-08-19	target/riscv: rationalise softfloat includes	Alex Bennée
2019-06-25	RISC-V: Clear load reservations on context switch and SC	Joel Sing
2019-06-25	RISC-V: Add support for the Zicsr extension	Palmer Dabbelt
2019-06-25	RISC-V: Add support for the Zifencei extension	Palmer Dabbelt
2019-06-25	target/riscv: Add support for disabling/enabling Counters	Alistair Francis
2019-06-25	target/riscv: Remove user version information	Alistair Francis
2019-06-25	target/riscv: Require either I or E base extension	Alistair Francis
2019-06-25	target/riscv: Set privledge spec 1.11.0 as default	Alistair Francis
2019-06-24	target/riscv: Restructure deprecatd CPUs	Alistair Francis
2019-06-23	target/riscv: Implement riscv_cpu_unassigned_access	Michael Clark
2019-06-23	target/riscv: Allow setting ISA extensions via CPU props	Alistair Francis
2019-06-11	qemu-common: Move qemu_isalnum() etc. to qemu/ctype.h	Markus Armbruster
2019-06-10	cpu: Introduce cpu_set_cpustate_pointers	Richard Henderson
2019-05-24	target/riscv: Add a base 32 and 64 bit CPU	Alistair Francis
2019-05-24	target/riscv: Create settable CPU properties	Alistair Francis
2019-05-24	target/riscv: Remove spaces from register names	Richard Henderson
2019-05-10	target/riscv: Convert to CPUClass::tlb_fill	Richard Henderson
2019-04-18	qom/cpu: Simplify how CPUClass:cpu_dump_state() prints	Markus Armbruster
2019-04-18	target: Simplify how the TARGET_cpu_list() print	Markus Armbruster
2019-03-19	target/riscv: Remove unused struct	Alistair Francis
2019-03-19	RISC-V: Add hooks to use the gdb xml files.	Jim Wilson
2019-02-11	RISC-V: Add misa runtime write support	Michael Clark
2019-01-09	RISC-V: Implement existential predicates for CSRs	Michael Clark
2018-12-20	riscv/cpu: use device_class_set_parent_realize	Mao Zhongyi
2018-10-17	RISC-V: Update CSR and interrupt definitions	Michael Clark
2018-05-18	target/riscv: Honor CPU_DUMP_FPU	Richard Henderson
2018-05-06	RISC-V: Update E and I extension order	Michael Clark
2018-03-28	RISC-V: Convert cpu definition to future model	Michael Clark