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path: root/target/riscv/cpu.c
AgeCommit message (Expand)Author
2023-01-20target/riscv/cpu.c: Fix elen checkDongxue Zhang
2023-01-06RISC-V: Add Zawrs ISA extension supportChristoph Muellner
2023-01-06target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()Bin Meng
2022-12-16target/riscv: Convert to 3-phase resetPeter Maydell
2022-10-26target/riscv: Convert to tcg_ops restore_state_to_opcRichard Henderson
2022-10-04accel/tcg: Introduce tb_pc and log_pcRichard Henderson
2022-10-04hw/core: Add CPUClass.get_pcRichard Henderson
2022-09-27target/riscv: Set the CPU resetvec directlyAlistair Francis
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra
2022-09-07target/riscv: Add stimecmp supportAtish Patra
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel
2022-09-07target/riscv: Add xicondops in ISA entryRahul Pathak
2022-09-07target/riscv: Add Zihintpause supportDao Lu
2022-09-07target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnosti...eopXD
2022-09-07target/riscv: Fix checks in hmode/hmode32Weiwei Li
2022-09-07target/riscv: H extension depends on I extensionWeiwei Li
2022-09-07target/riscv: Add check for supported privilege mode combinationsWeiwei Li
2022-09-07target/riscv: move zmmul out of the experimental propertiesWeiwei Li
2022-09-07target/riscv: Force disable extensions if priv spec version does not matchAnup Patel
2022-07-27RISC-V: Allow both Zmmul and MPalmer Dabbelt
2022-07-03target/riscv: Don't force update priv spec version to latestAnup Patel
2022-07-03target/riscv: Ibex: Support priv version 1.11Alistair Francis
2022-07-03target/riscv: pmu: Make number of counters configurableAtish Patra
2022-07-03target/riscv: pmu: Rename the counters extension to pmuAtish Patra
2022-06-10target/riscv: Don't expose the CPU properties on names CPUsAlistair Francis
2022-06-10target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnosti...eopXD
2022-06-10target/riscv: Wake on VS-level external interruptsAndrew Bresticker
2022-06-10target/riscv: add support for zmmul extension v0.1Weiwei Li
2022-05-24target/riscv: add zicsr/zifencei to isa_stringHongren (Zenithal) Zheng
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel
2022-05-24target/riscv: Fix typo of mimpid cpu optionFrank Chang
2022-05-24target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realizeWeiwei Li
2022-05-24target/riscv: Move/refactor ISA extension checksTsukasa OI
2022-05-24target/riscv: FP extension requirementsTsukasa OI
2022-05-24target/riscv: Change "G" expansionTsukasa OI
2022-05-24target/riscv: Disable "G" by defaultTsukasa OI
2022-05-24target/riscv: Fix coding style on "G" expansionTsukasa OI
2022-05-24target/riscv: Add short-isa-string optionTsukasa OI
2022-05-24target/riscv: Move Zhinx* extensions on ISA stringTsukasa OI
2022-04-29target/riscv: add scalar crypto related extenstion strings to isa_stringWeiwei Li
2022-04-29target/riscv: rvk: expose zbk* and zk* propertiesWeiwei Li
2022-04-29target/riscv: rvk: add cfg properties for zbk* and zk*Weiwei Li
2022-04-29target/riscv: Support configuarable marchid, mvendorid, mipid CSR valuesFrank Chang
2022-04-22target/riscv: cpu: Enable native debug featureBin Meng
2022-04-22target/riscv: csr: Hook debug CSR read/writeBin Meng
2022-04-22target/riscv: cpu: Add a config option for native debugBin Meng
2022-04-22target/riscv: debug: Implement debug related TCGCPUOpsBin Meng
2022-04-22target/riscv: Add isa extenstion strings to the device treeAtish Patra
2022-04-22target/riscv: misa to ISA string conversion fixTsukasa OI
2022-04-22target/riscv: Allow software access to MIP SEIPAlistair Francis
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