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path: root/target/riscv/cpu.c
AgeCommit message (Expand)Author
2020-07-02target/riscv: configure and turn on vector extension from command lineLIU Zhiwei
2020-07-02target/riscv: implementation-defined constant parametersLIU Zhiwei
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng
2020-06-19target/riscv: Rename IBEX CPU init routineBin Meng
2020-06-19riscv: Keep the CPU init routine names consistentBin Meng
2020-06-19riscv: Generalize CPU init routine for the imacu CPUBin Meng
2020-06-19riscv: Generalize CPU init routine for the gcsu CPUBin Meng
2020-06-19riscv: Generalize CPU init routine for the base CPUBin Meng
2020-06-08Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-re...Peter Maydell
2020-06-05target/riscv/cpu: Restrict CPU migration to system-modePhilippe Mathieu-Daudé
2020-06-03target/riscv: Add the lowRISC Ibex CPUAlistair Francis
2020-06-03target/riscv: Don't set PMP feature in the cpu initAlistair Francis
2020-06-03target/riscv: Disable the MMU correctlyAlistair Francis
2020-06-03target/riscv: Don't overwrite the reset vectorAlistair Francis
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis
2020-06-03target/riscv: Remove the deprecated CPUsAlistair Francis
2020-04-29target/riscv: Add a sifive-e34 cpu typeCorey Wharton
2020-03-17cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell
2020-03-05RISC-V: Add a missing "," in riscv_excp_namesPalmer Dabbelt
2020-02-27target/riscv: Allow enabling the Hypervisor extensionAlistair Francis
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis
2020-02-27target/riscv: Dump Hypervisor registers if enabledAlistair Francis
2020-02-27target/riscv: Rename the H irqs to VS irqsAlistair Francis
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis
2020-02-27target/riscv: Convert MIP CSR to target_ulongAlistair Francis
2020-01-24qdev: set properties with device_class_set_props()Marc-André Lureau
2020-01-24cpu: Use cpu_class_set_parent_reset()Greg Kurz
2019-11-14target/riscv: Remove atomic accesses to MIP CSRAlistair Francis
2019-10-28RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt
2019-09-17target/riscv: Use both register name and ABI nameAtish Patra
2019-08-19target/riscv: rationalise softfloat includesAlex Bennée
2019-06-25RISC-V: Clear load reservations on context switch and SCJoel Sing
2019-06-25RISC-V: Add support for the Zicsr extensionPalmer Dabbelt
2019-06-25RISC-V: Add support for the Zifencei extensionPalmer Dabbelt
2019-06-25target/riscv: Add support for disabling/enabling CountersAlistair Francis
2019-06-25target/riscv: Remove user version informationAlistair Francis
2019-06-25target/riscv: Require either I or E base extensionAlistair Francis
2019-06-25target/riscv: Set privledge spec 1.11.0 as defaultAlistair Francis
2019-06-24target/riscv: Restructure deprecatd CPUsAlistair Francis
2019-06-23target/riscv: Implement riscv_cpu_unassigned_accessMichael Clark
2019-06-23target/riscv: Allow setting ISA extensions via CPU propsAlistair Francis
2019-06-11qemu-common: Move qemu_isalnum() etc. to qemu/ctype.hMarkus Armbruster
2019-06-10cpu: Introduce cpu_set_cpustate_pointersRichard Henderson
2019-05-24target/riscv: Add a base 32 and 64 bit CPUAlistair Francis
2019-05-24target/riscv: Create settable CPU propertiesAlistair Francis
2019-05-24target/riscv: Remove spaces from register namesRichard Henderson
2019-05-10target/riscv: Convert to CPUClass::tlb_fillRichard Henderson
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster
2019-04-18target: Simplify how the TARGET_cpu_list() printMarkus Armbruster
2019-03-19target/riscv: Remove unused structAlistair Francis
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