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2024-04-02target/ppc: Rename init_excp_4xx_softmmu() -> init_excp_4xx()Philippe Mathieu-Daudé
Unify with other init_excp_FOO() in the same file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20240313213339.82071-5-philmd@linaro.org>
2024-03-30target/ppc: Do not clear MSR[ME] on MCE interrupts to supervisorNicholas Piggin
Hardware clears the MSR[ME] bit when delivering a machine check interrupt, so that is what QEMU does. The spapr environment runs in supervisor mode though, and receives machine check interrupts after they are processed by the hypervisor, and MSR[ME] must always be enabled in supervisor mode (otherwise it could checkstop the system). So MSR[ME] must not be cleared when delivering machine checks to the supervisor. The fix to prevent supervisor mode from modifying MSR[ME] also prevented it from re-enabling the incorrectly cleared MSR[ME] bit when returning from handling the interrupt. Before that fix, the problem was not very noticable with well-behaved code. So the Fixes tag is not strictly correct, but practically they go together. Found by kvm-unit-tests machine check tests (not yet upstream). Fixes: 678b6f1af75ef ("target/ppc: Prevent supervisor from modifying MSR[ME]") Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-30target/ppc: Fix GDB register indexing on secondary CPUsBenjamin Gray
The GDB server protocol assigns an arbitrary numbering of the SPRs. We track this correspondence on each SPR with gdb_id, using it to resolve any SPR requests GDB makes. Early on we generate an XML representation of the SPRs to give GDB, including this numbering. However the XML is cached globally, and we skip setting the SPR gdb_id values on subsequent threads if we detect it is cached. This causes QEMU to fail to resolve SPR requests against secondary CPUs because it cannot find the matching gdb_id value on that thread's SPRs. This is a minimal fix to first assign the gdb_id values, then return early if the XML is cached. Otherwise we generate the XML using the now already initialised gdb_id values. Fixes: 1b53948ff8f7 ("target/ppc: Use GDBFeature for dynamic XML") Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-30target/ppc: Restore [H]DEXCR to 64-bitsBenjamin Gray
The DEXCR emulation was recently changed to a 32-bit register, possibly because it does have a 32-bit read-only view. It is a full 64-bit SPR though, so use the corresponding 64-bit write functions. Fixes: fbda88f7abdee ("target/ppc: Fix width of some 32-bit SPRs") Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-30target/ppc/mmu-radix64: Use correct string format in walk_tree()Philippe Mathieu-Daudé
'mask', 'nlb' and 'base_addr' are all uin64_t types. Use the corresponding PRIx64 format. Fixes: d2066bc50d ("target/ppc: Check page dir/table base alignment") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13Merge tag 'pull-ppc-for-9.0-2-20240313' of https://gitlab.com/npiggin/qemu ↵Peter Maydell
into staging * PAPR nested hypervisor host implementation for spapr TCG * excp_helper.c code cleanups and improvements * Move more ops to decodetree * Deprecate pseries-2.12 machines and P9 and P10 DD1.0 CPUs * Document running Linux on AmigaNG * Update dt feature advertising POWER CPUs. * Add P10 PMU SPRs * Improve pnv topology calculation for SMT8 CPUs. * Various bug fixes. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEETkN92lZhb0MpsKeVZ7MCdqhiHK4FAmXwiT8ACgkQZ7MCdqhi # HK7C/w//XxEO2bQTFPLFDTrP/voq7pcX8XeQNVyXCkXYjvsbu05oQow50k+Y5UAE # US4MFjt8jFz0vuIKuKyoA3kG41zDSOzoX4TQXMM+tyTWbuFF3KAyfizb1xE6SYAN # xJEGvmiXv/EgoSBD7BTKQp1tMPdIGZLwSdYiA0lmOo7YaMCgYAXaujW5hnNjQecT # 873sN+10pHtQY++mINtD9Nfb6AcDGMWw0b+bykqIXhNRkI8IGOS4WF4vAuMBrwfe # UM00wDnNRb86Dk14bv2XVNDr6/i0VRtUMwM4yiptrQ1TQx18LZaPSQFYjQfPaan7 # LwN4QkMFnBX54yJ7Npvjvu8BCBF47kwOVu4CIAFJ4sIm0WfTmozDpPttwcZ5w7Ve # iXDOB9ECAB4pQ2rCgbSNG8MYUZgoHHOuThqolOP0Vh9NHRRJxpdw6CyAbmCGftc0 # lvRDPFiKp8xmCNJ/j3XzoUdHoG7NMwpUmHv9ruGU18SdQ8hyJN9AcQGWYrB4v0RV # /hs2RAbwntG7ahkcwd8uy5aFw88Wph/uGXPXc49EWj7i49vHeIV2y5+gtthMywje # qqjFXkistXuF+JHVnyoYmqqCyXaHX5CEwtawMv4EQeaJs76bLhMeMTKKl9rRp8qB # DtbIZphO8iMsocrBnje48sA5HR0PM+H4HTjw10i8R0fLlWitaIY= # =XnY5 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 12 Mar 2024 16:56:31 GMT # gpg: using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE # gpg: Good signature from "Nicholas Piggin <npiggin@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0 A795 67B3 0276 A862 1CAE * tag 'pull-ppc-for-9.0-2-20240313' of https://gitlab.com/npiggin/qemu: (38 commits) spapr: nested: Introduce cap-nested-papr for Nested PAPR API spapr: nested: Introduce H_GUEST_RUN_VCPU hcall. spapr: nested: Use correct source for parttbl info for nested PAPR API. spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls. spapr: nested: Initialize the GSB elements lookup table. spapr: nested: Extend nested_ppc_state for nested PAPR API spapr: nested: Introduce H_GUEST_CREATE_VCPU hcall. spapr: nested: Introduce H_GUEST_[CREATE|DELETE] hcalls. spapr: nested: Introduce H_GUEST_[GET|SET]_CAPABILITIES hcalls. spapr: nested: Document Nested PAPR API spapr: nested: keep nested-hv related code restricted to its API. spapr: nested: Introduce SpaprMachineStateNested to store related info. spapr: nested: move nested part of spapr_get_pate into spapr_nested.c spapr: nested: register nested-hv api hcalls only for cap-nested-hv target/ppc: Remove interrupt handler wrapper functions target/ppc: Clean up ifdefs in excp_helper.c, part 3 target/ppc: Clean up ifdefs in excp_helper.c, part 2 target/ppc: Clean up ifdefs in excp_helper.c, part 1 target/ppc: Add gen_exception_err_nip() function target/ppc: Readability improvements in exception handlers ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-13spapr: nested: Introduce H_GUEST_RUN_VCPU hcall.Harsh Prateek Bora
The H_GUEST_RUN_VCPU hcall is used to start execution of a Guest VCPU. The Hypervisor will update the state of the Guest VCPU based on the input buffer, restore the saved Guest VCPU state, and start its execution. The Guest VCPU can stop running for numerous reasons including HCALLs, hypervisor exceptions, or an outstanding Host Partition Interrupt. The reason that the Guest VCPU stopped running is communicated through R4 and the output buffer will be filled in with any relevant state. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13spapr: nested: Extend nested_ppc_state for nested PAPR APIHarsh Prateek Bora
Currently, nested_ppc_state stores a certain set of registers and works with nested_[load|save]_state() for state transfer as reqd for nested-hv API. Extending these with additional registers state as reqd for nested PAPR API. Acked-by: Nicholas Piggin <npiggin@gmail.com> Suggested-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13target/ppc: Remove interrupt handler wrapper functionsBALATON Zoltan
These wrappers call out to handle POWER7 and newer in separate functions but reduce to the generic case when TARGET_PPC64 is not defined. It is easy enough to include the switch in the beginning of the generic functions to branch out to the specific functions and get rid of these wrappers. This avoids one indirection and entirely compiles out the switch without TARGET_PPC64. Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13target/ppc: Clean up ifdefs in excp_helper.c, part 3BALATON Zoltan
Concatenate #if blocks that are ending then beginning on the next line again. Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13target/ppc: Clean up ifdefs in excp_helper.c, part 2BALATON Zoltan
Remove check for !defined(CONFIG_USER_ONLY) as this is already within an #ifndef CONFIG_USER_ONLY block. Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13target/ppc: Clean up ifdefs in excp_helper.c, part 1BALATON Zoltan
Use #ifdef, #ifndef for brevity and add comments to #endif that are more than a few lines apart for clarity. Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13target/ppc: Add gen_exception_err_nip() functionBALATON Zoltan
Add gen_exception_err_nip() that does the same as gen_exception_err() but takes the nip as a parameter to allow specifying it instead of using the current instruction address then change gen_exception_err() to use it. The gen_exception() and gen_exception_nip() functions are similar so remove code duplication from those too while at it. Suggested-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13target/ppc: Readability improvements in exception handlersBALATON Zoltan
Improve readability by shortening some long comments, removing comments that state the obvious and dropping some empty lines so they don't distract when reading the code. Acked-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13target/ppc: Use env_cpu for cpu_abort in excp_helperBALATON Zoltan
Use the env_cpu function to get the CPUState for cpu_abort. These are only needed in case of fatal errors so this allows to avoid casting and storing CPUState in a local variable wnen not needed. Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13ppc/pnv: Improve pervasive topology calculation for big-coreCaleb Schlossin
Big (SMT8) cores have a complicated function to map the core, thread ID to pervasive topology (PIR). Fix this for power8, power9, and power10. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Caleb Schlossin <calebs@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13target/ppc: Add power10 pmu SPRsMadhavan Srinivasan
Currently in tcg mode, when reading from power10 pmu spr like MMCR3, qemu logs this message (when starting qemu with -d guest_errors) Trying to read invalid spr 754 (0x2f2) at 0000000030056bb0 This is becuase, no read/write call-backs are registered for these SPRs. Add support to register generic read/write functions to these power10 pmu sprs to fix it. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13target/ppc: Move add and subf type fixed-point arithmetic instructions to ↵Chinmay Rath
decodetree This patch moves the below instructions to decodetree specification: {add, subf}[c,e,me,ze][o][.] : XO-form addic[.], subfic : D-form addex : Z23-form This patch introduces XO form instructions into decode tree specification, for which all the four variations([o][.]) have been handled with a single pattern. The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13target/ppc: POWER10 does not have transactional memoryNicholas Piggin
POWER10 hardware implements a degenerate transactional memory facility in POWER8/9 PCR compatibility modes to permit migration from older CPUs, but POWER10 / ISA v3.1 mode does not support it so the CPU model should not support it. Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13ppc: Drop support for POWER9 and POWER10 DD1 chipsNicholas Piggin
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of any use in QEMU. Remove them. Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13target/ppc: Prevent supervisor from modifying MSR[ME]Nicholas Piggin
Prevent guest state modifying the MSR[ME] bit. Per ISA: An attempt to modify MSR[ME] in privileged but non-hypervisor state is ignored (i.e., the bit is not changed). Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-13target/ppc: Fix GDB SPR regnum indexingNicholas Piggin
Fix an off by one bug. Fixes: 1b53948ff8f70 ("target/ppc: Use GDBFeature for dynamic XML") Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-03-12target/ppc: Prefer fast cpu_env() over slower CPU QOM cast macroPhilippe Mathieu-Daudé
Mechanical patch produced running the command documented in scripts/coccinelle/cpu_env.cocci_template header. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240129164514.73104-22-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-03-12target: Replace CPU_GET_CLASS(cpu -> obj) in cpu_reset_hold() handlerPhilippe Mathieu-Daudé
Since CPU() macro is a simple cast, the following are equivalent: Object *obj; CPUState *cs = CPU(obj) In order to ease static analysis when running scripts/coccinelle/cpu_env.cocci from the previous commit, replace: - CPU_GET_CLASS(cpu); + CPU_GET_CLASS(obj); Most code use the 'cs' variable name for CPUState handle. Replace few 's' -> 'cs' to unify cpu_reset_hold() style. No logical change in this patch. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240129164514.73104-7-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-03-12bulk: Access existing variables initialized to &S->F when availablePhilippe Mathieu-Daudé
When a variable is initialized to &struct->field, use it in place. Rationale: while this makes the code more concise, this also helps static analyzers. Mechanical change using the following Coccinelle spatch script: @@ type S, F; identifier s, m, v; @@ S *s; ... F *v = &s->m; <+... - &s->m + v ...+> Inspired-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240129164514.73104-2-philmd@linaro.org> Acked-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> [thuth: Dropped hunks that need a rebase, and fixed sizeof() in pmu_realize()] Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-02-29target/ppc: Enable TARGET_PAGE_BITS_VARY for user-onlyRichard Henderson
Since ppc binaries are generally built for multiple page sizes, it is trivial to allow the page size to vary. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20240102015808.132373-33-richard.henderson@linaro.org>
2024-02-28hw/core/cpu: Remove gdb_get_dynamic_xml memberAkihiko Odaki
This function is no longer used. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231213-gdb-v17-9-777047380591@daynix.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240227144335.1196131-14-alex.bennee@linaro.org>
2024-02-28gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cbAkihiko Odaki
Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the gdb_read_register and gdb_write_register members of CPUClass to allow to unify the logic to access registers of the core and coprocessors in the future. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231213-gdb-v17-6-777047380591@daynix.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240227144335.1196131-11-alex.bennee@linaro.org>
2024-02-28gdbstub: Use GDBFeature for gdb_register_coprocessorAkihiko Odaki
This is a tree-wide change to introduce GDBFeature parameter to gdb_register_coprocessor(). The new parameter just replaces num_regs and xml parameters for now. GDBFeature will be utilized to simplify XML lookup in a following change. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231213-gdb-v17-4-777047380591@daynix.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240227144335.1196131-9-alex.bennee@linaro.org>
2024-02-28target/ppc: Use GDBFeature for dynamic XMLAkihiko Odaki
In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231213-gdb-v17-2-777047380591@daynix.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240227144335.1196131-7-alex.bennee@linaro.org>
2024-02-24Merge tag 'pull-request-2024-02-23' of https://gitlab.com/thuth/qemu into ↵Peter Maydell
staging * m68k: Fix exception frame format for 68010 * Add cdrom test for LoongArch virt machine * Fix qtests when using --without-default-devices * Enable -Wvla * Windows 32-bit removal * Silence warnings in the test-x86-cpuid-compat qtest # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmXY7MMRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbWkRg//TCprQ7Gesex/yvMFIZuZk+poEaibxGXU # cWp6hneV8selTzBKzBC3VS1n31shd9astNRE95N2fSIfCV6R22y2tfZF2rSOoeog # bvqX7KoaEnSsrDS054EGAnuvYQpOGLGth/3Mc9Z791r5I1tYZPJocVnAyi/OB+3q # Gr5WzXj6Z/QD7c0f6vZ943wRBO/zc1729KikDUSyfS3Tua+15mAuUIUQdlLNNPct # 6aT5e6c967mAYh93AUevd3hgVYXH2W4fH7s1q2pap2hMBw2a43XvlMKJ9CvXPFPg # eU6knRPES16BSC2TTphNCBQi9n3rQdion01VsoQEetVBfFa4yA1Ys7ofF5vCa2l8 # 5EO5X3VQfZeq0ktmrLM7qAO0OMnolIqbeNS97ggOiyL0Q3YXim6cNWf8+OZbGoFR # OK88ndmzEXrZq+5w4QBDGLHFU3u8ZeWAM6p7Ht/ZN89ndDYT5bGBwkjVRW5hVgck # fmGhgutSqP2/DN5/4nMn8jtmGc65H/rBRilttW8W2JF72rQJYduDnx/A4KUatkHT # tC58NwLarF3kF7cebhWvNQDD74ia/35n+fEAmtIHF42YHE6aifss91QrgT+qGG5+ # GG12JIoFVDCgE1pkNU7GO53Uqo94Ej8TUOxwF9QfftxnqiktMG7Y/KQRcSA5VvHr # laagGgDzHP0= # =1hu9 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 23 Feb 2024 19:06:43 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2024-02-23' of https://gitlab.com/thuth/qemu: target/i386: do not filter processor tracing features except on KVM .gitlab-ci.d/windows.yml: Remove shared-msys2 abstraction .gitlab-ci.d: Drop cross-win32-system job docs: Document that 32-bit Windows is unsupported meson: Enable -Wvla target/ppc/kvm: Replace variable length array in kvmppc_read_hptes() target/ppc/kvm: Replace variable length array in kvmppc_save_htab() tests: skip dbus-display tests that need a console tests/qtest: Fix boot-serial-test when using --without-default-devices tests/cdrom-test: Add cdrom test for LoongArch virt machine target/m68k: Fix exception frame format for 68010 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-23target/ppc: optimise ppcemb_tlb_t flushingNicholas Piggin
Filter TLB flushing by PID and mmuidx. Zoltan reports that, together with the previous TLB flush changes, performance of a sam460ex machine running 'lame' to convert a wav to mp3 is improved nearly 10%: CPU time TLB partial flushes TLB elided flushes Before 37s 508238 7680722 After 34s 73 1143 Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23target/ppc: 440 optimise tlbwe TLB flushingNicholas Piggin
Have 440 tlbwe flush only the range corresponding to the addresses covered by the software TLB entry being modified rather than the entire TLB. This matches what 4xx does. Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23target/ppc: 4xx optimise tlbwe_lo TLB flushingNicholas Piggin
Rather than tlbwe_lo always flushing all TCG TLBs, have it flush just those corresponding to the old software TLB, and only if it was valid. Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23target/ppc: 4xx don't flush TLB for a newly written software TLB entryNicholas Piggin
BookE software TLB is implemented by flushing old translations from the relevant TCG TLB whenever software TLB entries change. This means a new software TLB entry should not have any corresponding cached TCG TLB translations, so there is nothing to flush. The exception is multiple software TLBs that cover the same address and address space, but that is a programming error and results in undefined behaviour, and flushing does not give an obviously better outcome in that case either. Remove the unnecessary flush of a newly written software TLB entry. Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23target/ppc: Factor out 4xx ppcemb_tlb_t flushingNicholas Piggin
Flushing the TCG TLB pages that cache a software TLB is a common operation, factor it into its own function. Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23target/ppc: Fix 440 tlbwe TLB invalidation gapsNicholas Piggin
The 440 tlbwe (write entry) instruction misses several cases that must flush the TCG TLB: - If the new size is smaller than the existing size, the EA no longer covered should be flushed. This looks like an inverted inequality test. - If the TLB PID changes. - If the TLB attr bit 0 (translation address space) changes. - If low prot (access control) bits change. Fix this by removing tricks to avoid TLB flushes, and just invalidate the TLB if any valid entry is being changed, similarly to 4xx. Optimisations will be introduced in subsequent changes. Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23target/ppc: Add SMT support to time facilitiesNicholas Piggin
The TB, VTB, PURR, HDEC SPRs are per-LPAR registers, and the TFMR is a per-core register. Add the necessary SMT synchronisation and value sharing. The TFMR can only drive the timebase state machine via thread 0 of the core, which is almost certainly not right, but it is enough for skiboot and certain other proprietary firmware. Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23target/ppc: Implement core timebase state machine and TFMRNicholas Piggin
This implements the core timebase state machine, which is the core side of the time-of-day system in POWER processors. This facility is operated by control fields in the TFMR register, which also contains status fields. The core timebase interacts with the chiptod hardware, primarily to receive TOD updates, to synchronise timebase with other cores. This model does not actually update TB values with TOD or updates received from the chiptod, as timebases are always synchronised. It does step through the states required to perform the update. There are several asynchronous state transitions. These are modelled using using mfTFMR to drive state changes, because it is expected that firmware poll the register to wait for those states. This is good enough to test basic firmware behaviour without adding real timers. The values chosen are arbitrary. Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23ppc/pnv: Implement the ChipTOD to Core transferNicholas Piggin
One of the functions of the ChipTOD is to transfer TOD to the Core (aka PC - Pervasive Core) timebase facility. The ChipTOD can be programmed with a target address to send the TOD value to. The hardware implementation seems to perform this by sending the TOD value to a SCOM address. This implementation grabs the core directly and manipulates the timebase facility state in the core. This is a hack, but it works enough for now. A better implementation would implement the transfer to the PnvCore xscom register and drive the timebase state machine from there. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23target/ppc: Fix move-to timebase SPR access permissionsNicholas Piggin
The move-to timebase registers TBU and TBL can not be read, and they can not be written in supervisor mode on hypervisor-capable CPUs. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23target/ppc: Improve timebase register defines namingNicholas Piggin
The timebase in ppc started out with the mftb instruction which is like mfspr but addressed timebase registers (TBRs) rather than SPRs. These instructions could be used to read TB and TBU at 268 and 269. Timebase could be written via the TBL and TBU SPRs at 284 and 285. The ISA changed around v2.03 to bring TB and TBU reads into the SPR space at 268 and 269 (access via mftb TBR-space is still supported but will be phased out). Later, VTB was added which is an entirely different register. The SPR number defines in QEMU are understandably inconsistently named. Change SPR 268, 269, 284, 285 to TBL, TBU, WR_TBL, WR_TBU, respectively. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23target/ppc: Rename TBL to TB on 64-bitNicholas Piggin
From the earliest PowerPC ISA, TBR (later SPR) 268 has been called TB and accessed with mftb instruction. The problem is that TB is the name of the 64-bit register, and 32-bit implementations can only read the lower half with one instruction, so 268 has also been called TBL and it does only read TBL on 32-bit. Change SPR 268 to be called TB on 64-bit implementations. Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/USaif Abrar
SPR's CFAR, DEC, HDEC, TB-L/U are not implemented as part of CPUPPCState. Hence, gdbstub is not able to access them using (CPUPPCState *)env->spr[] array. Update gdb_get_spr_reg() method to handle these SPR's specifically. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23hw/ppc/spapr_hcall: Allow elision of softmmu_resize_hpt_prepPhilippe Mathieu-Daudé
Check tcg_enabled() before calling softmmu_resize_hpt_prepare() and softmmu_resize_hpt_commit() to allow the compiler to elide their calls. The stubs are then unnecessary, remove them. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23target/ppc: Rename registers to match ISANicholas Piggin
Several registers have names that don't match the ISA (or convention with other QEMU PPC registers), making them unintuitive to use with GDB. Fortunately most of these registers are obscure and/or have not been correctly implemented in the gdb server (e.g., DEC, TB, CFAR), so risk of breaking users should be low. QEMU should follow the ISA for register name convention (where there is no established GDB name). Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23target/ppc: Fix crash on machine check caused by ifetchNicholas Piggin
is_prefix_insn_excp() loads the first word of the instruction address which caused an exception, to determine whether or not it was prefixed so the prefix bit can be set in [H]SRR1. This works if the instruction image can be loaded, but if the exception was caused by an ifetch, this load could fail and cause a recursive exception and crash. Machine checks caused by ifetch are not excluded from the prefix check and can crash (see issue 2108 for an example). Fix this by excluding machine checks caused by ifetch from the prefix check. Cc: qemu-stable@nongnu.org Acked-by: Cédric Le Goater <clg@kaod.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2108 Fixes: 55a7fa34f89 ("target/ppc: Machine check on invalid real address access on POWER9/10") Fixes: 5a5d3b23cb2 ("target/ppc: Add SRR1 prefix indication to interrupt handlers") Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23target/ppc: Fix lxv/stxv MSR facility checkNicholas Piggin
The move to decodetree flipped the inequality test for the VEC / VSX MSR facility check. This caused application crashes under Linux, where these facility unavailable interrupts are used for lazy-switching of VEC/VSX register sets. Getting the incorrect interrupt would result in wrong registers being loaded, potentially overwriting live values and/or exposing stale ones. Cc: qemu-stable@nongnu.org Reported-by: Joel Stanley <joel@jms.id.au> Fixes: 70426b5bb738 ("target/ppc: moved stxvx and lxvx from legacy to decodtree") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1769 Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Tested-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-02-23target/ppc/kvm: Replace variable length array in kvmppc_read_hptes()Thomas Huth
HPTES_PER_GROUP is 8 and HASH_PTE_SIZE_64 is 16, so we don't waste too many bytes by always allocating the maximum amount of bytes on the stack here to get rid of the variable length array. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240221162636.173136-3-thuth@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-02-23target/ppc/kvm: Replace variable length array in kvmppc_save_htab()Thomas Huth
To be able to compile QEMU with -Wvla (to prevent potential security issues), we need to get rid of the variable length array in the kvmppc_save_htab() function. Replace it with a heap allocation instead. Message-ID: <20240221162636.173136-2-thuth@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
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