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2022-02-18target/ppc: Add powerpc_reset_excp_state helperNicholas Piggin
This moves the logic to reset the QEMU exception state into its own function. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg: checkpatch fixes ] Message-Id: <20220216102545.1808018-8-npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: add helper for books vhyp hypercall handlerNicholas Piggin
The virtual hypervisor currently always intercepts and handles hypercalls but with a future change this will not always be the case. Add a helper for the test so the logic is abstracted from the mechanism. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20220216102545.1808018-7-npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: make vhyp get_pate method take lpid and return successNicholas Piggin
In prepartion for implementing a full partition table option for vhyp, update the get_pate method to take an lpid and return a success/fail indicator. The spapr implementation currently just asserts lpid is always 0 and always return success. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg: checkpatch fixes ] Message-Id: <20220216102545.1808018-6-npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: add vhyp addressing mode helper for radix MMUNicholas Piggin
The radix on vhyp MMU uses a single-level radix table walk, with the partition scope mapping provided by the flat QEMU machine memory. A subsequent change will use the two-level radix walk on vhyp in some situations, so provide a helper which can abstract that logic. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20220216102545.1808018-5-npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: raise HV interrupts for partition table entry problemsNicholas Piggin
Invalid or missing partition table entry exceptions should cause HV interrupts. HDSISR is set to bad MMU config, which is consistent with the ISA and experimentally matches what POWER9 generates. Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg: checkpatch fixes ] Message-Id: <20220216102545.1808018-2-npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Change VSX instructions behavior to fill with zerosVíctor Colombo
ISA v3.1 changed some VSX instructions behavior by changing what the other words/doubleword in the result should contain when the result is only one word/doubleword. e.g. xsmaxdp operates on doubleword 0 and saves the result also in doubleword 0. Before, the second doubleword result was undefined according to the ISA, but now it's stated that it should be zeroed. Even tough the result was undefined before, hardware implementing these instructions already filled these fields with 0s. Changing every ISA version in QEMU to this behavior makes the results match what happens in hardware. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220204181944.65063-1-victor.colombo@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: books: Remove excp_model argument from ppc_excp_apply_ailFabiano Rosas
We don't really need to check for exception model while applying AIL. We can check the lpcr_mask for the presence of LPCR_AIL/LPCR_HAIL. This removes one more instance of passing the exception model ID around. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220207183036.1507882-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Assert if MSR bits differ from msr_mask during exceptionsFabiano Rosas
We currently abort QEMU during the dispatch of an interrupt if we try to set MSR_HV without having MSR_HVB in the msr_mask. I think we should verify this for all MSR bits. There is no reason to ever have a MSR bit set if the corresponding bit is not set in that CPU's msr_mask. Note that this is not about the emulated code setting reserved bits. We clear the new_msr when starting to dispatch an exception, so if we end up with bits not present in the msr_mask that is a QEMU programming error. I kept the HSRR verification for BookS because it is the only CPU family that has HSRRs. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220207183036.1507882-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: powerpc_excp: Move common code to the caller functionFabiano Rosas
Make the cpu-specific powerpc_excp_* functions a bit simpler by moving the bounds check and logging to powerpc_excp. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220207183036.1507882-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Remove powerpc_excp_legacyFabiano Rosas
Now that all CPU families have their own separate exception dispatching code we can remove powerpc_excp_legacy. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220207183036.1507882-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 7xx: Set SRRs directly in exception codeFabiano Rosas
The 7xx CPUs don't have alternate/hypervisor Save and Restore Registers, so we can set SRR0 and SRR1 directly. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-11-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 7xx: Software TLB cleanupFabiano Rosas
This code applies only to the 7xx CPUs, so we can remove the switch statement. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-10-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 7xx: System Reset cleanupFabiano Rosas
Thre is no HV support in the 7xx. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-9-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 7xx: System Call exception cleanupFabiano Rosas
Remove the BookE code and add a comment explaining why we need to keep hypercall support even though this CPU does not have a hypervisor mode. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-8-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 7xx: Program exception cleanupFabiano Rosas
There's no ESR in the 7xx. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-7-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 7xx: External interrupt cleanupFabiano Rosas
There is no MSR_HV in the 7xx so remove the LPES0 handling. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 7xx: Machine Check exception cleanupFabiano Rosas
There's no MSR_HV in the 7xx. Also remove 40x and BookE code. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Simplify powerpc_excp_7xxFabiano Rosas
Differences from the generic powerpc_excp code: - Not BookE, so some MSR bits are cleared at interrupt dispatch; - No MSR_HV; - No power saving states; - No Hypervisor Emulation Assistance; - Not 64 bits; - No System call vectored; - No Alternate Interrupt Location. Exceptions used: POWERPC_EXCP_ALIGN POWERPC_EXCP_DECR POWERPC_EXCP_DLTLB POWERPC_EXCP_DSI POWERPC_EXCP_DSTLB POWERPC_EXCP_EXTERNAL POWERPC_EXCP_FPU POWERPC_EXCP_IABR POWERPC_EXCP_IFTLB POWERPC_EXCP_ISI POWERPC_EXCP_MCHECK POWERPC_EXCP_PERFM POWERPC_EXCP_PROGRAM POWERPC_EXCP_RESET POWERPC_EXCP_SMI POWERPC_EXCP_SYSCALL POWERPC_EXCP_THERM POWERPC_EXCP_TRACE Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Introduce powerpc_excp_7xxFabiano Rosas
Introduce a new powerpc_excp function specific for PowerPC 7xx CPUs (740, 745, 750, 750cl, 750cx, 750fx, 750gx, 755). This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Merge 7x5 and 7x0 exception model IDsFabiano Rosas
Since we've split the exception code by exception model, the exception model IDs are becoming less useful. These two can be merged. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: Set SRRs directly in exception codeFabiano Rosas
The 6xx CPUs don't have alternate/hypervisor Save and Restore Registers, so we can set SRR0 and SRR1 directly. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-12-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: Software TLB exceptions cleanupFabiano Rosas
This code applies only to the 6xx CPUs, so we can remove the switch statement. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-11-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: System Reset interrupt cleanupFabiano Rosas
There is no HV support in the 6xx. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-10-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: System Call exception cleanupFabiano Rosas
There is no Hypervisor mode in the 6xx CPUs. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-9-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: Program exception cleanupFabiano Rosas
There's no ESR in the 6xx CPUs. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-8-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: External interrupt cleanupFabiano Rosas
There's no Hypervisor mode in the 6xx, so remove all LPES0 logic. Also remove BookE IRQ code. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-7-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: Machine Check exception cleanupFabiano Rosas
There's no MSR_HV in the 6xx CPUs. Also remove the 40x and BookE code. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: 6xx: Critical exception cleanupFabiano Rosas
This only applies to the G2s, the other 6xx CPUs will not have this vector registered. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Simplify powerpc_excp_6xxFabiano Rosas
Differences from the generic powerpc_excp code: - Not BookE, so some MSR bits are cleared at interrupt dispatch; - No MSR_HV; - No power saving states; - No Hypervisor Emulation Assistance; - Not 64 bits; - No System call vectored; - No Alternate Interrupt Location. Exceptions used: POWERPC_EXCP_ALIGN POWERPC_EXCP_CRITICAL POWERPC_EXCP_DABR POWERPC_EXCP_DECR POWERPC_EXCP_DLTLB POWERPC_EXCP_DSI POWERPC_EXCP_DSTLB POWERPC_EXCP_DTLB POWERPC_EXCP_EXTERNAL POWERPC_EXCP_FPA POWERPC_EXCP_FPU POWERPC_EXCP_IABR POWERPC_EXCP_IFTLB POWERPC_EXCP_ISI POWERPC_EXCP_ITLB POWERPC_EXCP_MCHECK POWERPC_EXCP_MEXTBR POWERPC_EXCP_NMEXTBR POWERPC_EXCP_PROGRAM POWERPC_EXCP_RESET POWERPC_EXCP_SMI POWERPC_EXCP_SYSCALL POWERPC_EXCP_TRACE Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Introduce powerpc_excp_6xxFabiano Rosas
Introduce a new powerpc_excp function specific for PowerPC 6xx CPUs (603, 604, G2, MPC5xx, MCP8xx). This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Merge exception model IDs for 6xx CPUsFabiano Rosas
We don't need three separate exception model IDs for the 603, 604 and G2. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203200957.1434641-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Remove PowerPC 601 CPUsCédric Le Goater
The PowerPC 601 processor is the first generation of processors to implement the PowerPC architecture. It was designed as a bridge processor and also could execute most of the instructions of the previous POWER architecture. It was found on the first Macs and IBM RS/6000 workstations. There is not much interest in keeping the CPU model of this POWER-PowerPC bridge processor. We have the 603 and 604 CPU models of the 60x family which implement the complete PowerPC instruction set. Cc: "Hervé Poussineau" <hpoussin@reactos.org> Cc: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203142756.1302515-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Fix radix loggingCédric Le Goater
ppc_radix64_partition_scoped_xlate() logs the host page protection bits variable but it is uninitialized. The value is set later on in ppc_radix64_check_prot(). Remove the output. Fixes: Coverity CID 1468942 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Message-Id: <20220203142145.1301749-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: System Reset exception cleanupFabiano Rosas
There is no MSR_HV in BookE, so remove all of the HV logic. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-12-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: Watchdog Timer interruptFabiano Rosas
Remove the switch as this function applies to BookE only. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-11-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: System Call exception cleanupFabiano Rosas
QEMU does not support BookE as a hypervisor. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-10-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: Alignment interrupt cleanupFabiano Rosas
BookE has no DSISR or DAR. The proper registers ESR and DEAR were already set at this point. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-9-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: External interrupt cleanupFabiano Rosas
There is no LPES0 in BookE and no MSR_HV. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-8-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: Instruction storage exception cleanupFabiano Rosas
The SRR1 should be set to the MSR value. There are no diagnostic bits in the SRR1 for BookE. Note that this fixes a bug where MSR_GS would be set and Linux would go into KVM code when there's no KVM guest. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-7-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: Data Storage exception cleanupFabiano Rosas
There is no DSISR or DAR in BookE. Change to ESR and DEAR. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: Machine Check cleanupsFabiano Rosas
There's no MSR_HV in BookE. Also remove 40x code. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: booke: Critical exception cleanupFabiano Rosas
Remove 40x and G2 code. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Simplify powerpc_excp_bookeFabiano Rosas
Differences from the generic powerpc_excp code: - No MSR bits are cleared at interrupt dispatch; - No MSR_HV; - No power saving states; - No Hypervisor Emulation Assistance; - SPEU needs special handling; - Big endian only; - Both 64 and 32 bits; - No System call vectored; - No Alternate Interrupt Location. Exceptions used: POWERPC_EXCP_ALIGN POWERPC_EXCP_APU POWERPC_EXCP_CRITICAL POWERPC_EXCP_DEBUG POWERPC_EXCP_DECR POWERPC_EXCP_DSI POWERPC_EXCP_DTLB POWERPC_EXCP_EFPDI POWERPC_EXCP_EFPRI POWERPC_EXCP_EXTERNAL POWERPC_EXCP_FIT POWERPC_EXCP_FPU POWERPC_EXCP_ISI POWERPC_EXCP_ITLB POWERPC_EXCP_MCHECK POWERPC_EXCP_PROGRAM POWERPC_EXCP_RESET POWERPC_EXCP_SPEU POWERPC_EXCP_SYSCALL POWERPC_EXCP_WDT Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Introduce powerpc_excp_bookeFabiano Rosas
Introduce a new powerpc_excp function specific for BookE CPUs. This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220128224018.1228062-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-09target/ppc: Remove 440x4 CPUFabiano Rosas
This CPU was partially removed due to lack of support in 2017 by commit aef7796057 ("ppc: remove non implemented cpu models"). Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220128221611.1221715-1-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-31Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220130' into ↵Peter Maydell
staging ppc 7.0 queue: * Exception and TLB fixes for the 405 CPU (Fabiano and Cedric) * spapr fixes (Alexey and Daniel) * PowerNV PHB3/4 fixes (Frederic and Daniel) * PowerNV XIVE improvements (Cedric) * 603 CPUs fixes (Christophe) * Book-E exception fixes (Vitaly) * Misc compile issues (Philippe and Fabiano) * Exception model rework for the BookS CPUs (Fabiano) * Exception model rework for the 74xx CPUs (Fabiano) * Removal of 602 CPUs # gpg: Signature made Sun 30 Jan 2022 17:42:23 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-ppc-20220130: (41 commits) target/ppc: Remove support for the PowerPC 602 CPU target/ppc: 74xx: Set SRRs directly in exception code target/ppc: 74xx: System Reset interrupt cleanup target/ppc: 74xx: System Call exception cleanup target/ppc: 74xx: Program exception cleanup target/ppc: 74xx: External interrupt cleanup target/ppc: 74xx: Machine Check exception cleanup target/ppc: Simplify powerpc_excp_74xx target/ppc: Introduce powerpc_excp_74xx target/ppc: books: Program exception cleanup target/ppc: books: External interrupt cleanup target/ppc: books: Machine Check exception cleanup target/ppc: Simplify powerpc_excp_books target/ppc: Introduce powerpc_excp_books target/ppc: 405: Watchdog timer exception cleanup target/ppc: 405: Program exception cleanup target/ppc: 405: Instruction storage interrupt cleanup target/ppc: 405: Data Storage exception cleanup target/ppc: 405: Debug exception cleanup target/ppc: 405: Alignment exception cleanup ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-01-28target/ppc: Remove support for the PowerPC 602 CPUCédric Le Goater
The 602 was derived from the PowerPC 603, for the gaming market it seems. It was hardly used and no firmware supporting the CPU could be found. Drop support. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-28Remove unnecessary minimum_version_id_old fieldsPeter Maydell
The migration code will not look at a VMStateDescription's minimum_version_id_old field unless that VMSD has set the load_state_old field to something non-NULL. (The purpose of minimum_version_id_old is to specify what migration version is needed for the code in the function pointed to by load_state_old to be able to handle it on incoming migration.) We have exactly one VMSD which still has a load_state_old, in the PPC CPU; every other VMSD which sets minimum_version_id_old is doing so unnecessarily. Delete all the unnecessary ones. Commit created with: sed -i '/\.minimum_version_id_old/d' $(git grep -l '\.minimum_version_id_old') with the one legitimate use then hand-edited back in. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> --- It missed vmstate_ppc_cpu.
2022-01-28target/ppc: 74xx: Set SRRs directly in exception codeFabiano Rosas
The 74xx does not have alternate/hypervisor Save and Restore Registers, so we can set SRR0 and SRR1 directly. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220127201116.1154733-9-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-28target/ppc: 74xx: System Reset interrupt cleanupFabiano Rosas
The whole power saving states logic seems to be dependent on HV mode, which don't exist for 74xx so I'm removing it all and leaving the abort message. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220127201116.1154733-8-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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