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2017-02-22target-ppc: implement store atomic instructionBalamuruhan S
stwat: Store Word Atomic stdat: Store Doubleword Atomic The instruction includes as function code (5 bits) which gives a detail on the operation to be performed. The patch implements five such functions. Signed-off-by: Balamuruhan S <bala24@linux.vnet.ibm.com> Signed-off-by: Harish S <harisrir@linux.vnet.ibm.com> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> [ implement stdat, use macro and combine both implementation ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22target-ppc: implement load atomic instructionBalamuruhan S
lwat: Load Word Atomic ldat: Load Doubleword Atomic The instruction includes as function code (5 bits) which gives a detail on the operation to be performed. The patch implements five such functions. Signed-off-by: Balamuruhan S <bala24@linux.vnet.ibm.com> Signed-off-by: Harish S <harisrir@linux.vnet.ibm.com> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> [ combine both lwat/ldat implementation using macro ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22target-ppc: Add xsmaxjdp and xsminjdp instructionsBharata B Rao
xsmaxjdp: VSX Scalar Maximum Type-J Double-Precision xsminjdp: VSX Scalar Minimum Type-J Double-Precision Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22target-ppc: Add xsmaxcdp and xsmincdp instructionsBharata B Rao
xsmaxcdp: VSX Scalar Maximum Type-C Double-Precision xsmincdp: VSX Scalar Minimum Type-C Double-Precision Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22ppc: implement xssubqp instructionJose Ricardo Ziviani
xssubqp: VSX Scalar Subtract Quad-Precision. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22ppc: implement xssqrtqp instructionJose Ricardo Ziviani
xssqrtqp: VSX Scalar Square Root Quad-Precision. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22ppc: implement xsrqpxp instructionJose Ricardo Ziviani
xsrqpxp: VSX Scalar Round Quad-Precision to Double-Extended Precision. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22ppc: implement xsrqpi[x] instructionJose Ricardo Ziviani
xsrqpi[x]: VSX Scalar Round to Quad-Precision Integer [with Inexact]. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-02ppc/kvm: Handle the "family" CPU via alias instead of registering new typesThomas Huth
When running with KVM on POWER, we are registering a "family" CPU type for the host CPU that we are running on. For example, on all POWER8-compatible hosts, we register a "POWER8" CPU type, so that you can always start QEMU with "-cpu POWER8" there, without the need to know whether you are running on a POWER8, POWER8E or POWER8NVL host machine. However, we also have a "POWER8" CPU alias in the ppc_cpu_aliases list (that is mainly useful for TCG). This leads to two cosmetical drawbacks: If the user runs QEMU with "-cpu ?", we always claim that POWER8 is an "alias for POWER8_v2.0" - which is simply not true when running with KVM on POWER. And when using the 'query-cpu-definitions' QMP call, there are currently two entries for "POWER8", one for the alias, and one for the additional registered type. To solve the two problems, we should rather update the "family" alias instead of registering a new types. We then only have one "POWER8" CPU definition around, an alias, which also points to the right destination. Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1396536 Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-02target/ppc/mmu_hash64: Fix incorrect shift value in amr calculationSuraj Jitindar Singh
We are calculating the authority mask register key value wrong. The pte entry contains the key value with the two upper bits and the three lower bits stored separately. We should use these two portions to get a 5 bit value, not or them together which will only give us a 3 bit value. Fix this. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-02target/ppc/mmu_hash64: Fix printing unsigned as signed intSuraj Jitindar Singh
We were printing an unsigned value as a signed value, fix this. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-02tcg/POWER9: NOOP the cp_abort instructionSuraj Jitindar Singh
The cp_abort instruction is used to remove the state of an in progress copy paste sequence. POWER9 compilers add this in various places, such as context switches which causes illegal instruction signals since we don't yet implement this instruction. Given there is no implementation of the copy paste facility and that we don't claim to support it, we can just noop this instruction. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-02target/ppc/debug: Print LPCR register value if register existsSuraj Jitindar Singh
It can be useful when debugging to print the LPCR value. Thus we add the LPCR to the "info registers" output if the register had been defined. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-02target-ppc: Add xststdc[sp, dp, qp] instructionsNikunj A Dadhania
xststdcsp: VSX Scalar Test Data Class Single-Precision xststdcdp: VSX Scalar Test Data Class Double-Precision xststdcqp: VSX Scalar Test Data Class Quad-Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-02target-ppc: Add xvtstdc[sp,dp] instructionsNikunj A Dadhania
xvtstdcsp: VSX Vector Test Data Class Single-Precision xvtstdcdp: VSX Vector Test Data Class Double-Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target/ppc/cpu-models: Fix/remove bad CPU aliasesThomas Huth
There is no CPU model called "7447_v1.2" in our list, so the "7447" alias should point to "7447_v1.1" instead. Let's also remove the "codename" aliases that point to non-implemented CPU models - they are really of no use here. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target/ppc: Remove unused POWERPC_FAMILY(POWER)Thomas Huth
We do not support POWER1 CPUs in QEMU, so it does not make sense to keep this stub around. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31spapr: clock should count only if vm is runningLaurent Vivier
This is a port to ppc of the i386 commit: 00f4d64 kvmclock: clock should count only if vm is running We remove timebase_post_load function, and use the VM state change handler to save and restore the guest_timebase (on stop and continue). We keep timebase_pre_save to reduce the clock difference on migration like in: 6053a86 kvmclock: reduce kvmclock difference on migration Time base offset has originally been introduced by commit 98a8b52 spapr: Add support for time base offset migration So while VM is paused, the time is stopped. This allows to have the same result with date (based on Time Base Register) and hwclock (based on "get-time-of-day" RTAS call). Moreover in TCG mode, the Time Base is always paused, so this patch also adjust the behavior between TCG and KVM. VM state field "time_of_the_day_ns" is now useless but we keep it to be able to migrate to older version of the machine. As vmstate_ppc_timebase structure (with timebase_pre_save() and timebase_post_load() functions) was only used by vmstate_spapr, we register the VM state change handler only in ppc_spapr_init(). Signed-off-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target/ppc: Add pcr_supported to POWER9 cpu class definitionSuraj Jitindar Singh
pcr_supported is used to define the supported PCR values for a given processor. A POWER9 processor can support 3.00, 2.07, 2.06 and 2.05 compatibility modes, thus we set this accordingly. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31powerpc/cpu-models: rename ISAv3.00 logical PVR definitionSuraj Jitindar Singh
This logical PVR value now corresponds to ISA version 3.00 so rename it accordingly. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xvcv[hpsp, sphp] instructionsNikunj A Dadhania
xvcvhpsp: VSX Vector Convert Half Precision to Single Precision xvcvsphp: VSX Vector Convert Single Precision to Half Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xsmulqp instructionBharata B Rao
xsmulqp: VSX Scalar Multiply Quad-Precision Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xsdivqp instructionBharata B Rao
xsdivqp: VSX Scalar Divide Quad-Precision Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xscvsdqp and xscvudqp instructionsBharata B Rao
xscvsdqp: VSX Scalar Convert Signed Doubleword format to Quad-Precision format xscvudqp: VSX Scalar Convert Unsigned Doubleword format to Quad-Precision format Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Use ppc_vsr_t.f128 in xscmp[o,u,exp]qpBharata B Rao
xscmpoqp, xscmpuqp & xscmpexpqp were added before f128 field was introduced in ppc_vsr_t. Now that we have it, use it instead of generating the 128 bit float using two 64bit fields. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31ppc: Implement bcdutrunc. instructionJose Ricardo Ziviani
bcdutrunc. Decimal unsigned truncate. Works like bcdtrunc. with unsigned BCD numbers. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31ppc: Implement bcdtrunc. instructionJose Ricardo Ziviani
bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the number of bytes to truncate in vra, the return register will have vrb with such bits truncated. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xscvqps[d,w]z instructionsBharata B Rao
xscvqpsdz: VSX Scalar truncate & Convert Quad-Precision format to Signed Doubleword format xscvqpswz: VSX Scalar truncate & Convert Quad-Precision format to Signed Word format Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xvxsigdp instructionNikunj A Dadhania
xvxsigdp: VSX Vector Extract Significand Dual Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xvxsigsp instructionNikunj A Dadhania
xvxsigsp: VSX Vector Extract Significand Single Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xvxexpdp instructionNikunj A Dadhania
xvxexpdp: VSX Vector Extract Exponent Dual Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xvxexpsp instructionNikunj A Dadhania
xvxexpsp: VSX Vector Extract Exponent Single Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xviexpdp instructionNikunj A Dadhania
xviexpdp: VSX Vector Insert Exponent Dual Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xviexpsp instructionNikunj A Dadhania
xviexpsp: VSX Vector Insert Exponent Single Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xsiexpqp instructionNikunj A Dadhania
xsiexpqp: VSX Scalar Insert Exponent Quad Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xsiexpdp instructionNikunj A Dadhania
xsiexpdp: VSX Scalar Insert Exponent Double Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31ppc: Implement bcdsr. instructionJose Ricardo Ziviani
bcdsr.: Decimal shift and round. This instruction works like bcds. however, when performing right shift, 1 will be added to the result if the last digit was >= 5. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31ppc: Implement bcdus. instructionJose Ricardo Ziviani
bcdus.: Decimal unsigned shift. This instruction works like bcds. but considers only unsigned BCDs (no sign in least meaning 4 bits). Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31ppc: Implement bcds. instructionJose Ricardo Ziviani
bcds.: Decimal shift. Given two registers vra and vrb, this instruction shift the vrb value by vra bits into the result register. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: xscvqpdp zero VSRNikunj A Dadhania
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macroJose Ricardo Ziviani
This commit fixes a warning in the code "(i * 2) ? .. : ..", which should be better as "i ? .. : ..", and improves the BCD_DIG_BYTE macro by placing parentheses around its argument to avoid possible expansion issues like: BCD_DIG_BYTE(i + j). Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xscvqpdp instructionBharata B Rao
xscvqpdp: VSX Scalar round & Convert Quad-Precision format to Double-Precision format Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xscvdpqp instructionBharata B Rao
xscvdpqp: VSX Scalar Convert Double-Precision format to Quad-Precision format Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xsaddqp instructionsBharata B Rao
xsaddqp: VSX Scalar Add Quad-Precision Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31ppc: Add ppc_set_compat_all()David Gibson
Once a compatiblity mode is negotiated with the guest, h_client_architecture_support() uses run_on_cpu() to update each CPU to the new mode. We're going to want this logic somewhere else shortly, so make a helper function to do this global update. We put it in target-ppc/compat.c - it makes as much sense at the CPU level as it does at the machine level. We also move the cpu_synchronize_state() into ppc_set_compat(), since it doesn't really make any sense to call that without synchronizing state. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xsxsigqp instructionsNikunj A Dadhania
xsxsigqp: VSX Scalar Extract Significand Quad Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xsxsigdp instructionNikunj A Dadhania
xsxsigdp: VSX Scalar Extract Significand Dual Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xsxexpqp instructionNikunj A Dadhania
xsxexpqp: VSX Scalar Extract Exponent Quad Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xsxexpdp instructionNikunj A Dadhania
xsxexpdp: VSX Scalar Extract Exponent Dual Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Use correct precision for FPRF settingBharata B Rao
Use correct FP precision when setting FPRF in FP conversion helpers instead of always assuming float64 precision. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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