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2024-05-24target/ppc: Implement SPRC/SPRD SPRsNicholas Piggin
This implements the POWER SPRC/SPRD SPRs, and SCRATCH0-7 registers that can be accessed via these indirect SPRs. SCRATCH registers only provide storage, but they are used by firmware for low level crash and progress data, so this implementation logs writes to the registers to help with analysis. Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-05-24target/ppc: add helper to write per-LPAR SPRsNicholas Piggin
An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR means per-thread or per-core, depending on 1LPAR mode. Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-05-24target/ppc: Add PPR32 SPRNicholas Piggin
PPR32 provides access to the upper half of PPR. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-05-24target/ppc: Add new hflags to support BHRBGlenn Miles
This commit is preparatory to the addition of Branch History Rolling Buffer (BHRB) functionality, which is being provided today starting with the P8 processor. BHRB uses several SPR register fields to control whether or not a branch instruction's address (and sometimes target address) should be recorded. Checking each of these fields with each branch instruction using jitted code would lead to a significant decrease in performance. Therefore, it was decided that BHRB configuration bits that are not expected to change frequently should have their state summarized in an hflag so that the amount of checking done by jitted code can be reduced. This commit contains the changes for summarizing the state of the following register fields in the HFLAGS_BHRB_ENABLE hflag: MMCR0[FCP] - Determines if BHRB recording is frozen in the problem state MMCR0[FCPC] - A modifier for MMCR0[FCP] MMCRA[BHRBRD] - Disables all BHRB recording for a thread Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2023-09-06target/ppc: Implement watchpoint debug facility for v2.07SNicholas Piggin
ISA v2.07S introduced the watchpoint facility based on the DAWR0 and DAWRX0 SPRs. Implement this in TCG. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-09-06target/ppc: Implement breakpoint debug facility for v2.07SNicholas Piggin
ISA v2.07S introduced the breakpoint facility based on the CIABR SPR. Implement this in TCG. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-07-07target/ppc: SMT support for the HID SPRNicholas Piggin
HID is a per-core shared register, skiboot sets this (e.g., setting HILE) on one thread and that must affect all threads of the core. Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230705120631.27670-3-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Add TFMR SPR implementation with read and write helpersNicholas Piggin
TFMR is the Time Facility Management Register which is specific to POWER CPUs, and used for the purpose of timebase management (generally by firmware, not the OS). Add helpers for the TFMR register, which will form part of the core timebase facility model in future but for now behaviour is unchanged. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230625120317.13877-3-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-05-27target/ppc: Fix width of some 32-bit SPRsNicholas Piggin
Some 32-bit SPRs are incorrectly implemented as 64-bits on 64-bit targets. This changes VRSAVE, DSISR, HDSISR, DAWRX0, PIDR, LPIDR, DEXCR, HDEXCR, CTRL, TSCR, MMCRH, and PMC[1-6] from to be 32-bit registers. This only goes by the 32/64 classification in the architecture, it does not try to implement finer details of SPR implementation (e.g., not all bits implemented as simple read/write storage). Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Message-Id: <20230515092655.171206-2-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-12-21target/ppc: Implement the DEXCR and HDEXCRNicholas Miehlbradt
Define the DEXCR and HDEXCR as special purpose registers. Each register occupies two SPR indicies, one which can be read in an unprivileged state and one which can be modified in the appropriate priviliged state, however both indicies refer to the same underlying value. Note that the ISA uses the abbreviation UDEXCR in two different contexts: the userspace DEXCR, the SPR index which can be read from userspace (implemented in this patch), and the ultravisor DEXCR, the equivalent register for the ultravisor state (not implemented). Signed-off-by: Nicholas Miehlbradt <nicholas@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20221220042330.2387944-2-nicholas@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-02-18target/ppc: Move common SPR functions out of cpu_initFabiano Rosas
Let's leave cpu_init with just generic CPU initialization and QOM-related functions. The rest of the SPR registration functions will be moved in the following patches along with the code that uses them. These are only the commonly used ones. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-28-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Move SPR registration macros to a headerFabiano Rosas
Put the SPR registration macros in a header that is accessible outside of cpu_init.c. The following patches will move CPU-specific code to separate files and will need to access it. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-26-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: cpu_init: Expose some SPR registration helpersFabiano Rosas
The following patches will move CPU-specific code into separate files, so expose the most used SPR registration functions: register_sdr1_sprs | 22 callers register_low_BATs | 20 callers register_non_embedded_sprs | 19 callers register_high_BATs | 10 callers register_thrm_sprs | 8 callers register_usprgh_sprs | 6 callers register_6xx_7xx_soft_tlb | only 3 callers, but it helps to keep the soft TLB code consistent. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-25-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-18target/ppc: Rename spr_tcg.h to spr_common.hFabiano Rosas
Initial intent for the spr_tcg header was to expose the spr_read|write callbacks that are only used by TCG code. However, although these routines are TCG-specific, the KVM code needs access to env->sprs which creation is currently coupled to the callback registration. We are probably not going to decouple SPR creation and TCG callback registration any time soon, so let's rename the header to spr_common to accomodate the register_*_sprs functions that will be moved out of cpu_init.c in the following patches. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220216162426.1885923-24-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>