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path: root/target/ppc/fpu_helper.c
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2022-01-04target/ppc: do not silence snan in xscvspdpnMatheus Ferst
The non-signalling versions of VSX scalar convert to shorter/longer precision insns doesn't silence SNaNs in the hardware. To better match this behavior, use the non-arithmatic conversion of helper_todouble instead of float32_to_float64. A test is added to prevent future regressions. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211228120310.1957990-1-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: move xscvqpdp to decodetreeMatheus Ferst
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211213120958.24443-5-victor.colombo@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Fix xs{max, min}[cj]dp to use VSX registersVictor Colombo
PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using vector registers when they should be using VSX ones. This happens because the instructions are using GEN_VSX_HELPER_R3, which adds 32 to the register numbers, effectively making them vector registers. This patch fixes it by changing these instructions to use GEN_VSX_HELPER_X3. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20211213120958.24443-2-victor.colombo@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Use helper_todouble/tosingle in helper_xststdcspRichard Henderson
When computing the predicate "is this value currently formatted for single precision", we do not want to round the value according to the current rounding mode, nor perform a floating-point equality. We want to see if the N bits that make up single-precision are the only ones set within the register, and then a bitwise equality. Fixes a bug in which a single-precision NaN is considered !SP, because float64_eq(nan, nan) is always false. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-35-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Update fres to new flags and float64r32Richard Henderson
There is no double-rounding bug here, because the result is merely an estimate to within 1 part in 256, but perform the operation with float64r32_div for consistency. Use float_flag_invalid_snan instead of recomputing the snan-ness of the operand. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-34-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Add helper for frsqrtesRichard Henderson
There is no double-rounding bug here, because the result is merely an estimate to within 1 part in 32, but perform the operation with float64r32_div for consistency. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-33-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Add helper for fmulsRichard Henderson
Use float64r32_mul. Fixes a double-rounding issue with performing the compuation in float64 and then rounding afterward. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-32-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Add helpers for fadds, fsubs, fdivsRichard Henderson
Use float64r32_{add,sub,div}. Fixes a double-rounding issue with performing the compuation in float64 and then rounding afterward. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-31-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Add helper for fsqrtsRichard Henderson
Use float64r32_sqrt. Fixes a double-rounding issue with performing the compuation in float64 and then rounding afterward. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-30-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Add helpers for fmadds et alRichard Henderson
Use float64r32_muladd. Fixes a double-rounding issue with performing the compuation in float64 and then rounding afterward. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-29-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Update fre to new flagsRichard Henderson
Use float_flag_invalid_snan instead of recomputing the snan-ness of the operand. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-27-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Update xsrqpi and xsrqpxp to new flagsRichard Henderson
Use float_flag_invalid_snan instead of recomputing the snan-ness of the operand. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-26-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Update sqrt for new flagsRichard Henderson
Now that vxsqrt and vxsnan are computed directly by softfloat, we don't need to recompute it. Split out float_invalid_op_sqrt to be used in several places. This fixes VSX_SQRT, which did not order its tests correctly to eliminate NaN with sign set. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-25-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Use helper_todouble in do_frspRichard Henderson
We only needed one ieee arithmetic operation to raise exceptions. To convert back to register form, we can use our simpler non-arithmetic function. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-24-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Update do_frsp for new flagsRichard Henderson
Now that vxsnan is computed directly by softfloat, we don't need to recompute it. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-23-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Split out do_frspRichard Henderson
Calling helper_frsp directly from other helpers generates the incorrect retaddr. Split out a helper that takes the retaddr as a parameter. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-22-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Do not call do_float_check_status from do_fmaddRichard Henderson
We will process flags other than in valid in helper_float_check_status, which is invoked after the writeback to FRT. Fixes a bug in which FRT is not written when OE/UE/XE are enabled. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-21-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Split out do_fmaddRichard Henderson
Create a common function for all of the madd helpers. Let the compiler tail call or inline as it chooses. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-20-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Update fmadd for new flagsRichard Henderson
Now that vximz, vxisi, and vxsnan are computed directly by softfloat, we don't need to recompute it. This replaces the separate float{32,64}_maddsub_update_excp functions with a single float_invalid_op_madd function. Fix VSX_MADD by passing sfprf to float_invalid_op_madd, whereas the previous *_maddsub_update_excp assumed it true. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-19-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Clean up do_friRichard Henderson
Let float64_round_to_int detect and silence snans. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-18-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Tidy inexact handling in do_friRichard Henderson
In GEN_FLOAT_B, we called helper_reset_fpstatus immediately before calling helper_fri*. Therefore get_float_exception_flags is known to be zero, and this code can be simplified. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-17-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Use FloatRoundMode in do_friRichard Henderson
This is the proper type for the enumeration. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211119160502.17432-16-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Remove inline from do_friRichard Henderson
There's no reason the callers can't tail call to one function. Leave it up to the compiler either way. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211119160502.17432-15-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Fix VXCVI return valueRichard Henderson
We were returning nanval for any instance of invalid being set, but that is an incorrect for VXCVI. This failure can be seen in the float_convs tests. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-14-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Update float_invalid_cvt for new flagsRichard Henderson
Now that vxsnan is computed directly by softfloat, we don't need to recompute it via classes. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-13-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Move float_check_status from FPU_FCTI to translateRichard Henderson
Fixes a bug in which e.g XE enabled causes inexact to be raised before the writeback to the architectural register. All of the users of GEN_FLOAT_B either set set_fprf, or are one of the convert-to-integer instructions that require this behaviour. Split out the two gen_helper_* calls in gen_compute_fprf_float64 and protect only the first with set_fprf. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-12-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Update float_invalid_op_div for new flagsRichard Henderson
Now that vxidi, vxzdz, and vxsnan are computed directly by softfloat, we don't need to recompute it via classes. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-11-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Update float_invalid_op_mul for new flagsRichard Henderson
Now that vximz and vxsnan are computed directly by softfloat, we don't need to recompute it via classes. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-10-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Update float_invalid_op_addsub for new flagsRichard Henderson
Now that vxisi and vxsnan are computed directly by softfloat, we don't need to recompute it via classes. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-9-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Fixed call to deferred exceptionLucas Mateus Castro (alqotel)
mtfsf, mtfsfi and mtfsb1 instructions call helper_float_check_status after updating the value of FPSCR, but helper_float_check_status checks fp_status and fp_status isn't updated based on FPSCR and since the value of fp_status is reset earlier in the instruction, it's always 0. Because of this helper_float_check_status would change the FI bit to 0 as this bit checks if the last operation was inexact and float_flag_inexact is always 0. These instructions also don't throw exceptions correctly since helper_float_check_status throw exceptions based on fp_status. This commit created a new helper, helper_fpscr_check_status that checks FPSCR value instead of fp_status and checks for a larger variety of exceptions than do_float_check_status. Since fp_status isn't used, gen_reset_fpstatus() was removed. The hardware used to compare QEMU's behavior to was a Power9. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Message-Id: <20211201163808.440385-2-lucas.araujo@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-06-03target/ppc: overhauled and moved logic of storing fpscrBruno Larsen (billionai)
Followed the suggested overhaul to store_fpscr logic, and moved it to cpu.c where it can be accessed in !TCG builds. The overhaul was suggested because storing a value to fpscr should never raise an exception, so we could remove all the mess that happened with POWERPC_EXCP_FP. We also moved fpscr_set_rounding_mode into cpu.c as it could now be moved there, and it is needed when a value for the fpscr is being stored directly. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210527163522.23019-1-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-06-03target/ppc: reduce usage of fpscr_set_rounding_modeBruno Larsen (billionai)
It is preferable to store the current rounding mode and retore from that than recalculating from fpscr, so we changed the behavior of do_fri and VSX_ROUND to do it like that. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210521201759.85475-4-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-12-14ppc/translate: Raise exceptions after setting the ccGiuseppe Musacchio
The PowerISA reference states that the comparison operators update the FPCC, CR and FPSCR and, if VE=1, jump to the exception handler. Moving the exception-triggering code after the CC update sequence solves the problem. Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201112230130.65262-5-thatlemon@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-12-14ppc/translate: Delay NaN checking after comparisonGiuseppe Musacchio
Since we always perform a comparison between the two operands avoid checking for NaN unless the result states they're unordered. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201112230130.65262-4-thatlemon@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-12-14ppc/translate: Turn the helper macros into functionsGiuseppe Musacchio
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201112230130.65262-3-thatlemon@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-12-14ppc/translate: Fix unordered f64/f128 comparisonsGiuseppe Musacchio
According to the PowerISA v3.1 reference, Table 68 "Actions for xscmpudp - Part 1: Compare Unordered", whenever one of the two operands is a NaN the SO bit is set while the other three bits are cleared. Apply the same change to xscmpuqp. The respective ordered counterparts are unaffected. Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com> Message-Id: <20201112230130.65262-2-thatlemon@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-11-15powerpc tcg: Fix Lesser GPL version numberChetan Pant
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201019061126.3102-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-10-28ppc/: fix some comment spelling errorszhaolichang
I found that there are many spelling errors in the comments of qemu/target/ppc. I used spellcheck to check the spelling errors and found some errors in the folder. Signed-off-by: zhaolichang <zhaolichang@huawei.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Message-Id: <20201009064449.2336-3-zhaolichang@huawei.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-02-21target/ppc: Fix typo in commentsBALATON Zoltan
"Deferred" was misspelled as "differed" in some comments, correct this typo, Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <20200214155748.0896B745953@zero.eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-10-04ppc: Use FPSCR defines instead of constantsPaul A. Clarke
There are FPSCR-related defines in target/ppc/cpu.h which can be used in place of constants and explicit shifts which arguably improve the code a bit in places. Signed-off-by: Paul A. Clarke <pc@us.ibm.com> Message-Id: <1568817169-1721-1-git-send-email-pc@us.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-08-29target/ppc: Fix do_float_check_status vs inexactRichard Henderson
The underflow and inexact exceptions are not mutually exclusive. Check for both of them. Tidy the reset of FPSCR[FI]. Fixes: https://bugs.launchpad.net/bugs/1841442 Reported-by: Paul Clarke <pc@us.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Paul Clarke <pc@us.ibm.com> Message-Id: <20190826165434.18403-2-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-08-29ppc: Fix xscvdpspn for SNANPaul A. Clarke
The xscvdpspn instruction implements a non-arithmetic conversion. In particular, NaNs are not silenced and rounding is not performed. Rewrite to match the pseudocode for ConvertDPtoSP_NS() in the Power 3.0B manual. Signed-off-by: Paul A. Clarke <pc@us.ibm.com> Message-Id: <1566321964-1447-1-git-send-email-pc@us.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [dwg: Replaced description with clearer version from rth] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-08-21ppc: Fix emulated single to double denormalized conversionsPaul A. Clarke
helper_todouble() was not properly converting any denormalized 32 bit float to 64 bit double. Fix-suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paul A. Clarke <pc@us.ibm.com> v2: - Splitting patch "ppc: Three floating point fixes"; this is just one part. - Original suggested "fix" was likely flawed. v2 is rewritten by Richard Henderson (Thanks, Richard!); I reformatted the comments in a couple of places, compiled, and tested. Message-Id: <1566250936-14538-1-git-send-email-pc@us.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-08-21ppc: Fix emulated INFINITY and NAN conversionsPaul A. Clarke
helper_todouble() was not properly converting INFINITY from 32 bit float to 64 bit double. (Normalized operand conversion is unchanged, other than indentation.) Signed-off-by: Paul A. Clarke <pc@us.ibm.com> Message-Id: <1566242388-9244-1-git-send-email-pc@us.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-08-21ppc: conform to processor User's Manual for xscvdpspnPaul A. Clarke
The POWER8 and POWER9 User's Manuals specify the implementation behavior for what the ISA leaves "undefined" behavior for the xscvdpspn and xscvdpsp instructions. This patch corrects the QEMU implementation to match the hardware implementation for that case. ISA 3.0B has xscvdpspn leaving its result in word 0 of the target register, with the other words of the target register left "undefined". The User's Manuals specify: VSX scalar convert from double-precision to single-precision (xscvdpsp, xscvdpspn). VSR[32:63] is set to VSR[0:31]. So, words 0 and 1 both contain the result. Note: this is important because GCC as of version 8 or so, assumes and takes advantage of this behavior to optimize the following sequence: xscvdpspn vs0,vs1 mffprwz r8,f0 ISA 3.0B has xscvdpspn leaving its result in word 0 of the target register, and mffprwz expecting its input to come from word 1 of the source register. This sequence fails with QEMU, as a shift is required between those two instructions. However, since the hardware splats the result to both words 0 and 1 of its output register, the shift is not necessary. Expect a future revision of the ISA to specify this behavior. Signed-off-by: Paul A. Clarke <pc@us.ibm.com> v2 - Splitting patch "ppc: Three floating point fixes"; this is just one part. - Updated commit message to clarify behavior is documented in User's Manuals. - Updated commit message to correct which words are in output and source of xscvdpspn and mffprz. - No source changes to this part of the original patch. Message-Id: <1566236601-22954-1-git-send-email-pc@us.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-08-21ppc: Add support for 'mffsl' instructionPaul A. Clarke
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. This patch adds support for 'mffsl'. 'mffsl' is identical to 'mffs', except it only returns mode, status, and enable bits from the FPSCR. On CPUs without support for 'mffsl' (below ISA 3.0), the 'mffsl' instruction will execute identically to 'mffs'. Note: I renamed FPSCR_RN to FPSCR_RN0 so I could create an FPSCR_RN mask which is both bits of the FPSCR rounding mode, as defined in the ISA. I also fixed a typo in the definition of FPSCR_FR. Signed-off-by: Paul A. Clarke <pc@us.ibm.com> v4: - nit: added some braces to resolve a checkpatch complaint. v3: - Changed tcg_gen_and_i64 to tcg_gen_andi_i64, eliminating the need for a temporary, per review from Richard Henderson. v2: - I found that I copied too much of the 'mffs' implementation. The 'Rc' condition code bits are not needed for 'mffsl'. Removed. - I now free the (renamed) 'tmask' temporary. - I now bail early for older ISA to the original 'mffs' implementation. Message-Id: <1565982203-11048-1-git-send-email-pc@us.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-07-02target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macroMark Cave-Ayland
Introduce a new GEN_VSX_HELPER_VSX_MADD macro for the generator function which enables the source and destination registers to be decoded at translation time. This enables the determination of a or m form to be made at translation time so that a single helper function can now be used for both variants. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190616123751.781-16-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-07-02target/ppc: introduce GEN_VSX_HELPER_R2_AB macro to fpu_helper.cMark Cave-Ayland
Rather than perform the VSR register decoding within the helper itself, introduce a new GEN_VSX_HELPER_R2_AB macro which performs the decode based upon rA and rB at translation time. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190616123751.781-13-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-07-02target/ppc: introduce GEN_VSX_HELPER_R2 macro to fpu_helper.cMark Cave-Ayland
Rather than perform the VSR register decoding within the helper itself, introduce a new GEN_VSX_HELPER_R2 macro which performs the decode based upon rD and rB at translation time. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190616123751.781-12-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-07-02target/ppc: introduce GEN_VSX_HELPER_R3 macro to fpu_helper.cMark Cave-Ayland
Rather than perform the VSR register decoding within the helper itself, introduce a new GEN_VSX_HELPER_R3 macro which performs the decode based upon rD, rA and rB at translation time. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190616123751.781-11-mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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