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path: root/target/ppc/fpu_helper.c
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2017-03-06target/ppc: use helper for excp handlingNikunj A Dadhania
Use the helper routine float[32,64]_maddsub_update_excp() in VSX_MADD macro. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-06target/ppc: fmadd: add macro for updating flagsNikunj A Dadhania
Adds FPU_MADDSUB_UPDATE macro, this will be used for other routines having float32/16 Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-06target/ppc: fmadd check for excp independentlyNikunj A Dadhania
Current order of checking does not confirm with the spec (ISA 3.0: MultiplyAddDP page-469). Change the order and make them independent of each other. For example: a = infinity, b = zero, c = SNaN, this should set both VXIMZ and VXNAN Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-03-03target/ppc: rewrite f[n]m[add,sub] using float64_muladdNikunj A Dadhania
Use the softfloat api for fused multiply-add. Introduce routine to set the FPSCR flags VXNAN, VXIMZ nad VMISI. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22target-ppc: Add xscvqpudz and xscvqpuwz instructionsBharata B Rao
xscvqpudz: VSX Scalar truncate & Convert Quad-Precision format to Unsigned Doubleword format xscvqpuwz: VSX Scalar truncate & Convert Quad-Precision format to Unsigned Word format Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22target-ppc: Implement round to odd variants of quad FP instructionsBharata B Rao
xsaddqpo: VSX Scalar Add Quad-Precision using round to Odd xsmulqo: VSX Scalar Multiply Quad-Precision using round to Odd xsdivqpo: VSX Scalar Divide Quad-Precision using round to Odd xscvqpdpo: VSX Scalar round & Convert Quad-Precision format to Double-Precision format using round to Odd xssqrtqpo: VSX Scalar Square Root Quad-Precision using round to Odd xssubqpo: VSX Scalar Subtract Quad-Precision using round to Odd In addition, fix the invalid bitmask in the instruction encoding of xssqrtqp[o]. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> CC: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22target-ppc: Add xsmaxjdp and xsminjdp instructionsBharata B Rao
xsmaxjdp: VSX Scalar Maximum Type-J Double-Precision xsminjdp: VSX Scalar Minimum Type-J Double-Precision Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22target-ppc: Add xsmaxcdp and xsmincdp instructionsBharata B Rao
xsmaxcdp: VSX Scalar Maximum Type-C Double-Precision xsmincdp: VSX Scalar Minimum Type-C Double-Precision Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22ppc: implement xssubqp instructionJose Ricardo Ziviani
xssubqp: VSX Scalar Subtract Quad-Precision. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22ppc: implement xssqrtqp instructionJose Ricardo Ziviani
xssqrtqp: VSX Scalar Square Root Quad-Precision. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22ppc: implement xsrqpxp instructionJose Ricardo Ziviani
xsrqpxp: VSX Scalar Round Quad-Precision to Double-Extended Precision. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-22ppc: implement xsrqpi[x] instructionJose Ricardo Ziviani
xsrqpi[x]: VSX Scalar Round to Quad-Precision Integer [with Inexact]. Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-02target-ppc: Add xststdc[sp, dp, qp] instructionsNikunj A Dadhania
xststdcsp: VSX Scalar Test Data Class Single-Precision xststdcdp: VSX Scalar Test Data Class Double-Precision xststdcqp: VSX Scalar Test Data Class Quad-Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-02target-ppc: Add xvtstdc[sp,dp] instructionsNikunj A Dadhania
xvtstdcsp: VSX Vector Test Data Class Single-Precision xvtstdcdp: VSX Vector Test Data Class Double-Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xvcv[hpsp, sphp] instructionsNikunj A Dadhania
xvcvhpsp: VSX Vector Convert Half Precision to Single Precision xvcvsphp: VSX Vector Convert Single Precision to Half Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xsmulqp instructionBharata B Rao
xsmulqp: VSX Scalar Multiply Quad-Precision Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xsdivqp instructionBharata B Rao
xsdivqp: VSX Scalar Divide Quad-Precision Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xscvsdqp and xscvudqp instructionsBharata B Rao
xscvsdqp: VSX Scalar Convert Signed Doubleword format to Quad-Precision format xscvudqp: VSX Scalar Convert Unsigned Doubleword format to Quad-Precision format Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Use ppc_vsr_t.f128 in xscmp[o,u,exp]qpBharata B Rao
xscmpoqp, xscmpuqp & xscmpexpqp were added before f128 field was introduced in ppc_vsr_t. Now that we have it, use it instead of generating the 128 bit float using two 64bit fields. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xscvqps[d,w]z instructionsBharata B Rao
xscvqpsdz: VSX Scalar truncate & Convert Quad-Precision format to Signed Doubleword format xscvqpswz: VSX Scalar truncate & Convert Quad-Precision format to Signed Word format Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xvxsigsp instructionNikunj A Dadhania
xvxsigsp: VSX Vector Extract Significand Single Precision Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: xscvqpdp zero VSRNikunj A Dadhania
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xscvqpdp instructionBharata B Rao
xscvqpdp: VSX Scalar round & Convert Quad-Precision format to Double-Precision format Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xscvdpqp instructionBharata B Rao
xscvdpqp: VSX Scalar Convert Double-Precision format to Quad-Precision format Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xsaddqp instructionsBharata B Rao
xsaddqp: VSX Scalar Add Quad-Precision Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Use correct precision for FPRF settingBharata B Rao
Use correct FP precision when setting FPRF in FP conversion helpers instead of always assuming float64 precision. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xscvdphp, xscvhpdpBharata B Rao
xscvdphp: VSX Scalar round & Convert Double-Precision format to Half-Precision format xscvhpdp: VSX Scalar Convert Half-Precision format to Double-Precision format Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64Bharata B Rao
Since helper_compute_fprf() works on float64 argument, rename it to helper_compute_fprf_float64(). Also use a macro to generate helper_compute_fprf_float64() so that float128 version of the same helper can be introduced easily later. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Replace isden by float64_is_zero_or_denormalBharata B Rao
Replace isden() by float64_is_zero_or_denormal() so that code in helper_compute_fprf() can be reused to work with float128 argument. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Use float64 arg in helper_compute_fprf()Bharata B Rao
Use float64 argument instead of unit64_t in helper_compute_fprf() This allows code in helper_compute_fprf() to be reused later to work with float128 argument too. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xxperm and xxpermr instructionsBharata B Rao
xxperm: VSX Vector Permute xxpermr: VSX Vector Permute Right-indexed Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: move ppc_vsr_t to common headerNikunj A Dadhania
The structure and corresponding defines and functions need to be used outside of fpu_helper.c as well. Add u8, u16, u32 and Int128 to the structure. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xscmpoqp and xscmpuqp instructionsBharata B Rao
xscmpoqp - VSX Scalar Compare Ordered Quad-Precision xscmpuqp - VSX Scalar Compare Unordered Quad-Precision Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Add xscmpexp[dp,qp] instructionsBharata B Rao
xscmpexpdp: VSX Scalar Compare Exponents Double-Precision xscmpexpqp: VSX Scalar Compare Exponents Quad-Precision Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Fix xscmpodp and xscmpudp instructionsBharata B Rao
- xscmpodp & xscmpudp are missing flags reset. - In xscmpodp, VXCC should be set only if VE is 0 for signalling NaN case and VXCC should be set by explicitly checking for quiet NaN case. - Comparison is being done only if the operands are not NaNs. However as per ISA, it should be done even when operands are NaNs. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31target-ppc: Consolidate instruction decode helpersBharata B Rao
Move instruction decode helpers to target-ppc/internal.h so that some of these can be used from outside of translate.c. This movement also helps to get rid of some duplicate helpers from target-ppc/fpu_helper.c. Suggested-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-12-20Move target-* CPU file into a target/ folderThomas Huth
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
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