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QEMU is a generic and open source machine & userspace emulator and virtualizer
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openrisc
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Author
2018-11-27
vmstate: constify VMStateField
Marc-André Lureau
2018-10-31
decodetree: Remove "insn" argument from trans_* expanders
Richard Henderson
2018-07-03
target/openrisc: Fix writes to interrupt mask register
Stafford Horne
2018-07-03
target/openrisc: Fix delay slot exception flag to match spec
Stafford Horne
2018-07-03
linux-user: Implement signals for openrisc
Richard Henderson
2018-07-03
target/openrisc: Reorg tlb lookup
Richard Henderson
2018-07-03
target/openrisc: Increase the TLB size
Richard Henderson
2018-07-03
target/openrisc: Stub out handle_mmu_fault for softmmu
Richard Henderson
2018-07-03
target/openrisc: Use identical sizes for ITLB and DTLB
Richard Henderson
2018-07-03
target/openrisc: Fix cpu_mmu_index
Richard Henderson
2018-07-03
target/openrisc: Fix tlb flushing in mtspr
Richard Henderson
2018-07-03
target/openrisc: Reduce tlb to a single dimension
Richard Henderson
2018-07-03
target/openrisc: Merge mmu_helper.c into mmu.c
Richard Henderson
2018-07-03
target/openrisc: Remove indirect function calls for mmu
Richard Henderson
2018-07-03
target/openrisc: Merge tlb allocation into CPUOpenRISCState
Richard Henderson
2018-07-03
target/openrisc: Form the spr index from tcg
Richard Henderson
2018-07-03
target/openrisc: Exit the TB after l.mtspr
Richard Henderson
2018-07-03
target/openrisc: Split out is_user
Richard Henderson
2018-07-03
target/openrisc: Link more translation blocks
Richard Henderson
2018-07-03
target/openrisc: Fix singlestep_enabled
Richard Henderson
2018-07-03
target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB
Richard Henderson
2018-07-03
target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP
Richard Henderson
2018-07-03
target/openrisc: Log interrupts
Richard Henderson
2018-07-03
target/openrisc: Add print_insn_or1k
Richard Henderson
2018-07-02
target/openrisc: Fix mtspr shadow gprs
Richard Henderson
2018-06-04
Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into st...
Peter Maydell
2018-06-01
tcg: Pass tb and index to tcg_gen_exit_tb separately
Richard Henderson
2018-06-01
target: Do not include "exec/exec-all.h" if it is not necessary
Philippe Mathieu-Daudé
2018-05-14
target/openrisc: Merge disas_openrisc_insn
Richard Henderson
2018-05-14
target/openrisc: Convert dec_float
Richard Henderson
2018-05-14
target/openrisc: Convert dec_compi
Richard Henderson
2018-05-14
target/openrisc: Convert dec_comp
Richard Henderson
2018-05-14
target/openrisc: Convert dec_M
Richard Henderson
2018-05-14
target/openrisc: Convert dec_logic
Richard Henderson
2018-05-14
target/openrisc: Convert dec_mac
Richard Henderson
2018-05-14
target/openrisc: Convert dec_calc
Richard Henderson
2018-05-14
target/openrisc: Convert remainder of dec_misc insns
Richard Henderson
2018-05-14
target/openrisc: Convert memory insns
Richard Henderson
2018-05-14
target/openrisc: Convert branch insns
Richard Henderson
2018-05-14
target/openrisc: Start conversion to decodetree.py
Richard Henderson
2018-05-14
target-openrisc: Write back result before FPE exception
Richard Henderson
2018-05-09
target/openrisc: convert to TranslatorOps
Emilio G. Cota
2018-05-09
target/openrisc: convert to DisasContextBase
Emilio G. Cota
2018-04-11
icount: fix cpu_restore_state_from_tb for non-tb-exit cases
Pavel Dovgalyuk
2018-03-19
cpu: get rid of unused cpu_init() defines
Igor Mammedov
2018-03-19
cpu: add CPU_RESOLVING_TYPE macro
Igor Mammedov
2018-02-21
target/*/cpu.h: remove softfloat.h
Alex Bennée
2018-02-05
qdev: use device_class_set_parent_realize/unrealize/reset()
Philippe Mathieu-Daudé
2018-01-25
accel/tcg: add size paremeter in tlb_fill()
Laurent Vivier
2017-12-27
target/*helper: don't check retaddr before calling cpu_restore_state
Alex Bennée
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