aboutsummaryrefslogtreecommitdiff
path: root/target/openrisc
AgeCommit message (Expand)Author
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée
2018-02-05qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier
2017-12-27target/*helper: don't check retaddr before calling cpu_restore_stateAlex Bennée
2017-12-18misc: remove duplicated includesPhilippe Mathieu-Daudé
2017-10-30Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell
2017-10-27openrisc: cleanup cpu type name compositionIgor Mammedov
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell
2017-10-25disas: Remove unused flags argumentsRichard Henderson
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson
2017-10-21openrisc/cputimer: Perparation for MulticoreStafford Horne
2017-10-21target/openrisc: Make coreid and numcores variableStafford Horne
2017-10-09qom/cpu: move cpu_model null check to cpu_class_by_name()Philippe Mathieu-Daudé
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova
2017-09-01openrisc: replace cpu_openrisc_init() with cpu_generic_init()Igor Mammedov
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova
2017-05-04target/openrisc: Support non-busy idle state using PMR SPRStafford Horne
2017-05-04target/openrisc: Remove duplicate features propertyStafford Horne
2017-05-04target/openrisc: Implement full vmstate serializationStafford Horne
2017-05-04target/openrisc: implement shadow registersStafford Horne
2017-05-04target/openrisc: add numcores and coreid supportStafford Horne
2017-05-04target/openrisc: Fixes for memory debuggingStafford Horne
2017-04-21target/openrisc: Implement EPH bitTim 'mithro' Ansell
2017-04-21target/openrisc: Implement EVBAR registerTim 'mithro' Ansell
2017-02-14target/openrisc: Optimize for r0 being zeroRichard Henderson
2017-02-14target/openrisc: Tidy handling of delayed branchesRichard Henderson
2017-02-14target/openrisc: Tidy ppc/npc implementationRichard Henderson
2017-02-14target/openrisc: Optimize l.jal to nextRichard Henderson
2017-02-14target/openrisc: Fix maddRichard Henderson
2017-02-14target/openrisc: Implement muld, muldu, macu, msbuRichard Henderson
2017-02-14target/openrisc: Represent MACHI:MACLO as a single unitRichard Henderson
2017-02-14target/openrisc: Implement msyncRichard Henderson
2017-02-14target/openrisc: Enable trap, csync, msync, psync for user modeRichard Henderson
2017-02-14target/openrisc: Set flags on helpersRichard Henderson
2017-02-14target/openrisc: Use movcond where appropriateRichard Henderson
2017-02-14target/openrisc: Keep SR_CY and SR_OV in a separate variablesRichard Henderson
2017-02-14target/openrisc: Keep SR_F in a separate variableRichard Henderson
2017-02-14target/openrisc: Invert the decoding in dec_calcRichard Henderson
2017-02-14target/openrisc: Put SR[OVE] in TB flagsRichard Henderson
2017-02-14target/openrisc: Streamline arithmetic and OVERichard Henderson
2017-02-14target/openrisc: Rationalize immediate extractionRichard Henderson
2017-02-14target/openrisc: Tidy insn dumpingRichard Henderson
2017-02-14target/openrisc: Implement lwa, swaRichard Henderson
2017-02-14target/openrisc: Fix exception handling status registersStafford Horne
2017-02-14target/openrisc: Rename the cpu from or32 to or1kRichard Henderson
2017-01-13cputlb: drop flush_global flag from tlb_flushAlex Bennée
2017-01-13qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée