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AgeCommit message (Expand)Author
2017-02-14target/openrisc: Optimize for r0 being zeroRichard Henderson
2017-02-14target/openrisc: Tidy handling of delayed branchesRichard Henderson
2017-02-14target/openrisc: Tidy ppc/npc implementationRichard Henderson
2017-02-14target/openrisc: Optimize l.jal to nextRichard Henderson
2017-02-14target/openrisc: Fix maddRichard Henderson
2017-02-14target/openrisc: Implement muld, muldu, macu, msbuRichard Henderson
2017-02-14target/openrisc: Represent MACHI:MACLO as a single unitRichard Henderson
2017-02-14target/openrisc: Implement msyncRichard Henderson
2017-02-14target/openrisc: Enable trap, csync, msync, psync for user modeRichard Henderson
2017-02-14target/openrisc: Set flags on helpersRichard Henderson
2017-02-14target/openrisc: Use movcond where appropriateRichard Henderson
2017-02-14target/openrisc: Keep SR_CY and SR_OV in a separate variablesRichard Henderson
2017-02-14target/openrisc: Keep SR_F in a separate variableRichard Henderson
2017-02-14target/openrisc: Invert the decoding in dec_calcRichard Henderson
2017-02-14target/openrisc: Put SR[OVE] in TB flagsRichard Henderson
2017-02-14target/openrisc: Streamline arithmetic and OVERichard Henderson
2017-02-14target/openrisc: Rationalize immediate extractionRichard Henderson
2017-02-14target/openrisc: Tidy insn dumpingRichard Henderson
2017-02-14target/openrisc: Implement lwa, swaRichard Henderson
2017-02-14target/openrisc: Fix exception handling status registersStafford Horne
2017-02-14target/openrisc: Rename the cpu from or32 to or1kRichard Henderson
2017-01-13cputlb: drop flush_global flag from tlb_flushAlex Bennée
2017-01-13qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée
2017-01-10target-openrisc: Use clz and ctz opcodesRichard Henderson
2016-12-20Move target-* CPU file into a target/ folderThomas Huth