Age | Commit message (Expand) | Author |
2017-05-04 | target/openrisc: Support non-busy idle state using PMR SPR | Stafford Horne |
2017-05-04 | target/openrisc: Remove duplicate features property | Stafford Horne |
2017-05-04 | target/openrisc: Implement full vmstate serialization | Stafford Horne |
2017-05-04 | target/openrisc: implement shadow registers | Stafford Horne |
2017-05-04 | target/openrisc: add numcores and coreid support | Stafford Horne |
2017-05-04 | target/openrisc: Fixes for memory debugging | Stafford Horne |
2017-04-21 | target/openrisc: Implement EPH bit | Tim 'mithro' Ansell |
2017-04-21 | target/openrisc: Implement EVBAR register | Tim 'mithro' Ansell |
2017-02-14 | target/openrisc: Optimize for r0 being zero | Richard Henderson |
2017-02-14 | target/openrisc: Tidy handling of delayed branches | Richard Henderson |
2017-02-14 | target/openrisc: Tidy ppc/npc implementation | Richard Henderson |
2017-02-14 | target/openrisc: Optimize l.jal to next | Richard Henderson |
2017-02-14 | target/openrisc: Fix madd | Richard Henderson |
2017-02-14 | target/openrisc: Implement muld, muldu, macu, msbu | Richard Henderson |
2017-02-14 | target/openrisc: Represent MACHI:MACLO as a single unit | Richard Henderson |
2017-02-14 | target/openrisc: Implement msync | Richard Henderson |
2017-02-14 | target/openrisc: Enable trap, csync, msync, psync for user mode | Richard Henderson |
2017-02-14 | target/openrisc: Set flags on helpers | Richard Henderson |
2017-02-14 | target/openrisc: Use movcond where appropriate | Richard Henderson |
2017-02-14 | target/openrisc: Keep SR_CY and SR_OV in a separate variables | Richard Henderson |
2017-02-14 | target/openrisc: Keep SR_F in a separate variable | Richard Henderson |
2017-02-14 | target/openrisc: Invert the decoding in dec_calc | Richard Henderson |
2017-02-14 | target/openrisc: Put SR[OVE] in TB flags | Richard Henderson |
2017-02-14 | target/openrisc: Streamline arithmetic and OVE | Richard Henderson |
2017-02-14 | target/openrisc: Rationalize immediate extraction | Richard Henderson |
2017-02-14 | target/openrisc: Tidy insn dumping | Richard Henderson |
2017-02-14 | target/openrisc: Implement lwa, swa | Richard Henderson |
2017-02-14 | target/openrisc: Fix exception handling status registers | Stafford Horne |
2017-02-14 | target/openrisc: Rename the cpu from or32 to or1k | Richard Henderson |
2017-01-13 | cputlb: drop flush_global flag from tlb_flush | Alex Bennée |
2017-01-13 | qom/cpu: move tlb_flush to cpu_common_reset | Alex Bennée |
2017-01-10 | target-openrisc: Use clz and ctz opcodes | Richard Henderson |
2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth |