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path: root/target/openrisc/translate.c
AgeCommit message (Expand)Author
2020-08-21meson: targetPaolo Bonzini
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé
2019-10-28target/openrisc: fetch code with translator_ldEmilio G. Cota
2019-09-04target/openrisc: Implement l.adrpRichard Henderson
2019-09-04target/openrisc: Implement unordered fp comparisonsRichard Henderson
2019-09-04target/openrisc: Add support for ORFPX64A32Richard Henderson
2019-09-04target/openrisc: Check CPUCFG_OF32S for float insnsRichard Henderson
2019-09-04target/openrisc: Cache R0 in DisasContextRichard Henderson
2019-09-04target/openrisc: Replace cpu register array with a functionRichard Henderson
2019-09-04target/openrisc: Add DisasContext parameter to check_r0_writeRichard Henderson
2019-09-03tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster
2019-01-30target/openrisc: Fix LGPL version numberThomas Huth
2018-10-31decodetree: Remove "insn" argument from trans_* expandersRichard Henderson
2018-07-03target/openrisc: Fix cpu_mmu_indexRichard Henderson
2018-07-03target/openrisc: Form the spr index from tcgRichard Henderson
2018-07-03target/openrisc: Exit the TB after l.mtsprRichard Henderson
2018-07-03target/openrisc: Split out is_userRichard Henderson
2018-07-03target/openrisc: Link more translation blocksRichard Henderson
2018-07-03target/openrisc: Fix singlestep_enabledRichard Henderson
2018-07-03target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTBRichard Henderson
2018-07-03target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMPRichard Henderson
2018-07-03target/openrisc: Add print_insn_or1kRichard Henderson
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson
2018-05-14target/openrisc: Merge disas_openrisc_insnRichard Henderson
2018-05-14target/openrisc: Convert dec_floatRichard Henderson
2018-05-14target/openrisc: Convert dec_compiRichard Henderson
2018-05-14target/openrisc: Convert dec_compRichard Henderson
2018-05-14target/openrisc: Convert dec_MRichard Henderson
2018-05-14target/openrisc: Convert dec_logicRichard Henderson
2018-05-14target/openrisc: Convert dec_macRichard Henderson
2018-05-14target/openrisc: Convert dec_calcRichard Henderson
2018-05-14target/openrisc: Convert remainder of dec_misc insnsRichard Henderson
2018-05-14target/openrisc: Convert memory insnsRichard Henderson
2018-05-14target/openrisc: Convert branch insnsRichard Henderson
2018-05-14target/openrisc: Start conversion to decodetree.pyRichard Henderson
2018-05-14target-openrisc: Write back result before FPE exceptionRichard Henderson
2018-05-09target/openrisc: convert to TranslatorOpsEmilio G. Cota
2018-05-09target/openrisc: convert to DisasContextBaseEmilio G. Cota
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell
2017-10-25disas: Remove unused flags argumentsRichard Henderson
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova
2017-05-04target/openrisc: implement shadow registersStafford Horne
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