| Age | Commit message (Expand) | Author |
|---|
| 2023-09-29 | target/mips: Clean up local variable shadowing | Philippe Mathieu-Daudé |
| 2023-09-28 | accel/tcg: Always require can_do_io | Richard Henderson |
| 2023-08-31 | hw/mips: spelling fixes | Michael Tokarev |
| 2023-08-31 | target/mips: Remove unused headers in lcsr_helper.c | Philippe Mathieu-Daudé |
| 2023-08-31 | target/helpers: Remove unnecessary 'qemu/main-loop.h' header | Philippe Mathieu-Daudé |
| 2023-08-31 | target/helpers: Remove unnecessary 'exec/cpu_ldst.h' header | Philippe Mathieu-Daudé |
| 2023-08-31 | target/translate: Include missing 'exec/cpu_ldst.h' header | Philippe Mathieu-Daudé |
| 2023-08-31 | bulk: Do not declare function prototypes using 'extern' keyword | Philippe Mathieu-Daudé |
| 2023-08-22 | mips: Report an error when KVM_VM_MIPS_VZ is unavailable | Akihiko Odaki |
| 2023-08-22 | kvm: Introduce kvm_arch_get_default_type hook | Akihiko Odaki |
| 2023-07-25 | target/mips: Avoid shift by negative number in page_table_walk_refill() | Peter Maydell |
| 2023-07-25 | target/mips: Pass directory/leaf shift values to walk_directory() | Philippe Mathieu-Daudé |
| 2023-07-25 | target/mips/mxu: Avoid overrun in gen_mxu_q8adde() | Philippe Mathieu-Daudé |
| 2023-07-25 | target/mips/mxu: Avoid overrun in gen_mxu_S32SLT() | Philippe Mathieu-Daudé |
| 2023-07-25 | target/mips/mxu: Replace magic array size by its definition | Philippe Mathieu-Daudé |
| 2023-07-10 | target/mips: enable GINVx support for I6400 and I6500 | Marcin Nowakowski |
| 2023-07-10 | target/mips/mxu: Add Q8SAD instruction | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add S32SFL instruction | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add Q8MADL instruction | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add Q16SCOP instruction | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add Q8MAC Q8MACSU instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add D32/Q16- SLLV/SLRV/SARV instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add Q16SLL Q16SLR Q16SAR instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add D32SLL D32SLR D32SAR instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add D32SARL D32SARW instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add S32ALN S32LUI insns | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insns | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add S16LDD S16STD S16LDI S16SDI instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add S8STD S8LDI S8SDI instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add Q8ADDE Q8ACCE D8SUM D8SUMC instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add Q16ACC Q16ACCM D16ASUM instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add D32ADDC instruction | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add D32ACC D32ACCM D32ASUM instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add D32ADD instruction | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add Q16ADD instruction | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add S16MAD instruction | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add D16MADL instruction | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add D16MACF D16MACE instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add D16MULF D16MULE instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add S32CPS D16CPS Q8ABD Q16SAT insns | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add Q8ADD instruction | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add S32SLT D16SLT D16AVG[R] Q8AVG[R] insns | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Fix D16MAX D16MIN Q8MAX Q8MIN instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add Q8SLT Q8SLTU instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add S32MADD/MADDU/MSUB/MSUBU instructions | Siarhei Volkau |
| 2023-07-10 | target/mips/mxu: Add LXW LXB LXH LXBU LXHU instructions | Siarhei Volkau |
| 2023-07-10 | target/mips: Add support of two XBurst CPUs | Siarhei Volkau |
| 2023-07-10 | target/mips: Add emulation of MXU instructions for 32-bit load/store | Siarhei Volkau |
| 2023-07-10 | target/mips: Implement Loongson CSR instructions | Jiaxun Yang |
