| Age | Commit message (Expand) | Author |
|---|
| 2017-08-02 | target/mips: Fix RDHWR CC with icount | James Hogan |
| 2017-08-02 | target/mips: Drop redundant gen_io_start/stop() | James Hogan |
| 2017-08-02 | target/mips: Use BS_EXCP where interrupts are expected | James Hogan |
| 2017-08-02 | target-mips: apply CP0.PageMask before writing into TLB entry | Leon Alrae |
| 2017-08-02 | mips: Add KVM T&E segment support for TCG | James Hogan |
| 2017-08-02 | mips: Improve segment defs for KVM T&E guests | James Hogan |
| 2017-08-02 | target-mips: Don't stop on [d]mtc0 DESAVE/KScratch | James Hogan |
| 2017-07-31 | docs: fix broken paths to docs/devel/tracing.txt | Philippe Mathieu-Daudé |
| 2017-07-21 | target/mips: Enable CP0_EBase.WG on MIPS64 CPUs | James Hogan |
| 2017-07-21 | target/mips: Add EVA support to P5600 | James Hogan |
| 2017-07-20 | target/mips: Implement segmentation control | James Hogan |
| 2017-07-20 | target/mips: Add segmentation control registers | James Hogan |
| 2017-07-20 | target/mips: Add an MMU mode for ERL | James Hogan |
| 2017-07-20 | target/mips: Abstract mmu_idx from hflags | James Hogan |
| 2017-07-20 | target/mips: Check memory permissions with mem_idx | James Hogan |
| 2017-07-20 | target/mips: Decode microMIPS EVA load & store instructions | James Hogan |
| 2017-07-20 | target/mips: Decode MIPS32 EVA load & store instructions | James Hogan |
| 2017-07-20 | target/mips: Prepare loads/stores for EVA | James Hogan |
| 2017-07-20 | target/mips: Add CP0_Ebase.WG (write gate) support | James Hogan |
| 2017-07-20 | target/mips: Weaken TLB flush on UX,SX,KX,ASID changes | James Hogan |
| 2017-07-20 | target/mips: Fix TLBWI shadow flush for EHINV,XI,RI | James Hogan |
| 2017-07-20 | target/mips: Fix MIPS64 MFC0 UserLocal on BE host | James Hogan |
| 2017-07-19 | tcg: Pass generic CPUState to gen_intermediate_code() | Lluís Vilanova |
| 2017-07-17 | target/mips: optimize WSBH, DSBH and DSHD | Aurelien Jarno |
| 2017-07-17 | mips: set CP0 Debug DExcCode for SDBBP instruction | Pavel Dovgalyuk |
| 2017-07-11 | target/mips: fix msa copy_[s|u]_df rd = 0 corner case | Miodrag Dinic |
| 2017-07-04 | vcpu_dirty: share the same field in CPUState for all accelerators | Sergio Andres Gomez Del Real |
| 2017-06-05 | target/mips: optimize indirect branches | Aurelien Jarno |
| 2017-06-05 | target/mips: optimize cross-page direct jumps in softmmu | Aurelien Jarno |
| 2017-03-20 | target/mips: fix delay slot detection in gen_msa_branch() | Yongbok Kim |
| 2017-03-20 | target-mips: replace few LOG_DISAS() with trace points | Philippe Mathieu-Daudé |
| 2017-03-20 | target-mips: replace break by goto cp0_unimplemented | Philippe Mathieu-Daudé |
| 2017-03-20 | target-mips: log bad coprocessor0 register accesses with LOG_UNIMP | Philippe Mathieu-Daudé |
| 2017-03-20 | target-mips: remove old & unuseful comments | Philippe Mathieu-Daudé |
| 2017-03-20 | target-mips: fix compiler warnings (clang 5) | Philippe Mathieu-Daudé |
| 2017-03-09 | target/mips: hold BQL for timer interrupts | Yongbok Kim |
| 2017-03-03 | KVM: do not use sigtimedwait to catch SIGBUS | Paolo Bonzini |
| 2017-03-03 | KVM: remove kvm_arch_on_sigbus | Paolo Bonzini |
| 2017-02-21 | target-mips: Provide function to test if a CPU supports an ISA | Paul Burton |
| 2017-01-24 | migration: extend VMStateInfo | Jianjun Duan |
| 2017-01-20 | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging | Peter Maydell |
| 2017-01-16 | stubs: remove stubs/kvm.c | Paolo Bonzini |
| 2017-01-13 | cputlb: drop flush_global flag from tlb_flush | Alex Bennée |
| 2017-01-13 | qom/cpu: move tlb_flush to cpu_common_reset | Alex Bennée |
| 2017-01-10 | target-mips: Use clz opcode | Richard Henderson |
| 2017-01-10 | target-mips: Use the new extract op | Richard Henderson |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth |
