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2021-08-25target/mips: Introduce generic TRANS() macro for decodetree helpersPhilippe Mathieu-Daudé
Plain copy/paste of the TRANS() macro introduced in the PPC commit f2aabda8ac9 ("target/ppc: Move D/DS/X-form integer loads to decodetree") to the MIPS target. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210808173018.90960-2-f4bug@amsat.org>
2021-08-25target/mips: Rename 'rtype' as 'r'Philippe Mathieu-Daudé
We'll soon have more opcode and decoded arguments, and 'rtype' is not very helpful. Naming it simply 'r' ease reviewing the .decode files when we have many opcodes. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-5-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25target/mips: Merge 32-bit/64-bit Release6 decodetree definitionsPhilippe Mathieu-Daudé
We don't need to maintain 2 sets of decodetree definitions. Merge them into a single file. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-4-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25target/mips: Decode vendor extensions before MIPS ISAsPhilippe Mathieu-Daudé
In commit ffc672aa977 ("target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree") we misplaced the decoder call. Move it to the correct place. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-3-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25target/mips: Simplify PREF opcodePhilippe Mathieu-Daudé
check_insn() checks for any bit in the set, and INSN_R5900 is just another bit added to the set. No need to special-case it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-2-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25target/mips: Remove JR opcode unused argumentsPhilippe Mathieu-Daudé
JR opcode (Jump Register) only takes 1 argument, $rs. JALR (Jump And Link Register) takes 3: $rs, $rd and $hint. Commit 6af0bf9c7c3 added their processing into decode_opc() as: case 0x08 ... 0x09: /* Jumps */ gen_compute_branch(ctx, op1 | EXT_SPECIAL, rs, rd, sa); having both opcodes handled in the same function: gen_compute_branch. Per JR encoding, both $rd and $hint ('sa') are decoded as zero. Later this code got extracted to decode_opc_special(), commit 7a387fffce5 used definitions instead of magic values: case OPC_JR ... OPC_JALR: gen_compute_branch(ctx, op1, rs, rd, sa); Finally commit 0aefa33318b moved OPC_JR out of decode_opc_special, to a new 'decode_opc_special_legacy' function: @@ -15851,6 +15851,9 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) + case OPC_JR: + gen_compute_branch(ctx, op1, 4, rs, rd, sa); + break; @@ -15933,7 +15936,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) - case OPC_JR ... OPC_JALR: + case OPC_JALR: gen_compute_branch(ctx, op1, 4, rs, rd, sa); break; Since JR is now handled individually, it is pointless to decode and pass it unused arguments. Replace them by simple zero value to avoid confusion with this opcode. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210730225507.2642827-1-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson
The hook is now unused, with breakpoints checked outside translation. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-12Merge remote-tracking branch 'remotes/philmd/tags/mips-20210711' into stagingPeter Maydell
MIPS patches queue - Rename Raven ASIC PCI bridge, add PCI_IO_BASE_ADDR definition - Various Toshiba TX79 opcodes implemented - Rewrite UHI errno_mips() using switch statement - Few fixes and improvements in the SONIC model (dp8393x) # gpg: Signature made Sun 11 Jul 2021 22:12:49 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/mips-20210711: dp8393x: don't force 32-bit register access dp8393x: Rewrite dp8393x_get() / dp8393x_put() dp8393x: Store CAM registers as 16-bit dp8393x: Replace 0x40 magic value by SONIC_REG_COUNT definition dp8393x: Replace address_space_rw(is_write=1) by address_space_write() dp8393x: fix CAM descriptor entry index target/mips: Rewrite UHI errno_mips() using switch statement target/mips/tx79: Introduce SQ opcode (Store Quadword) target/mips/tx79: Introduce LQ opcode (Load Quadword) target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words) target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word) target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than) target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal) target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower) target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word) target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract) target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic) hw/pci-host/raven: Add PCI_IO_BASE_ADDR definition hw/pci-host: Rename Raven ASIC PCI bridge as raven.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-07-12Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' ↵Peter Maydell
into staging Add translator_use_goto_tb. Cleanups in prep of breakpoint fixes. Misc fixes. # gpg: Signature made Sat 10 Jul 2021 16:29:14 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210710: (41 commits) cpu: Add breakpoint tracepoints tcg: Remove TCG_TARGET_HAS_goto_ptr accel/tcg: Log tb->cflags with -d exec accel/tcg: Split out log_cpu_exec accel/tcg: Move tb_lookup to cpu-exec.c accel/tcg: Move helper_lookup_tb_ptr to cpu-exec.c target/i386: Use cpu_breakpoint_test in breakpoint_handler tcg: Fix prologue disassembly target/xtensa: Use translator_use_goto_tb target/tricore: Use tcg_gen_lookup_and_goto_ptr target/tricore: Use translator_use_goto_tb target/sparc: Use translator_use_goto_tb target/sh4: Use translator_use_goto_tb target/s390x: Remove use_exit_tb target/s390x: Use translator_use_goto_tb target/rx: Use translator_use_goto_tb target/riscv: Use translator_use_goto_tb target/ppc: Use translator_use_goto_tb target/openrisc: Use translator_use_goto_tb target/nios2: Use translator_use_goto_tb ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-07-11target/mips: Rewrite UHI errno_mips() using switch statementPhilippe Mathieu-Daudé
Linking on Haiku OS fails: /boot/system/develop/tools/bin/../lib/gcc/x86_64-unknown-haiku/8.3.0/../../../../x86_64-unknown-haiku/bin/ld: error: libqemu-mips-softmmu.fa.p/target_mips_tcg_sysemu_mips-semi.c.o(.rodata) is too large (0xffff405a bytes) /boot/system/develop/tools/bin/../lib/gcc/x86_64-unknown-haiku/8.3.0/../../../../x86_64-unknown-haiku/bin/ld: final link failed: memory exhausted collect2: error: ld returned 1 exit status This is because the host_to_mips_errno[] uses errno as index, for example: static const uint16_t host_to_mips_errno[] = { [ENAMETOOLONG] = 91, ... and Haiku defines [*] ENAMETOOLONG as: 12 /* Error baselines */ 13 #define B_GENERAL_ERROR_BASE INT_MIN .. 22 #define B_STORAGE_ERROR_BASE (B_GENERAL_ERROR_BASE + 0x6000) ... 106 #define B_NAME_TOO_LONG (B_STORAGE_ERROR_BASE + 4) ... 211 #define ENAMETOOLONG B_TO_POSIX_ERROR(B_NAME_TOO_LONG) so the array ends up beeing indeed too big. Since POSIX errno can't be use as indexes on Haiku, rewrite errno_mips() using a switch statement. [*] https://github.com/haiku/haiku/blob/r1beta3/headers/os/support/Errors.h#L130 Reported-by: Richard Zak <richard.j.zak@gmail.com> Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210706130723.1178961-1-f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce SQ opcode (Store Quadword)Philippe Mathieu-Daudé
Introduce the SQ opcode (Store Quadword). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-27-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce LQ opcode (Load Quadword)Philippe Mathieu-Daudé
Introduce the LQ opcode (Load Quadword) and remove unreachable code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-26-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)Philippe Mathieu-Daudé
Introduce the PROT3W opcode (Parallel Rotate 3 Words). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-25-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)Philippe Mathieu-Daudé
Introduce the PPACW opcode (Parallel Pack to Word). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-22-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)Philippe Mathieu-Daudé
Introduce the 'Parallel Compare for Greater Than' opcodes: - PCGTB (Parallel Compare for Greater Than Byte) - PCGTH (Parallel Compare for Greater Than Halfword) - PCGTW (Parallel Compare for Greater Than Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-15-f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)Philippe Mathieu-Daudé
Introduce the 'Parallel Compare for Equal' opcodes: - PCEQB (Parallel Compare for Equal Byte) - PCEQH (Parallel Compare for Equal Halfword) - PCEQW (Parallel Compare for Equal Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-14-f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower)Philippe Mathieu-Daudé
Introduce the 'Parallel Extend Lower' opcodes: - PEXTLB (Parallel Extend Upper from Byte) - PEXTLH (Parallel Extend Upper from Halfword) - PEXTLW (Parallel Extend Upper from Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-13-f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)Philippe Mathieu-Daudé
Introduce the PEXTUW opcode (Parallel Extend Upper from Word). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-12-f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)Philippe Mathieu-Daudé
Introduce the 'Parallel Subtract' opcodes: - PSUBB (Parallel Subtract Byte) - PSUBH (Parallel Subtract Halfword) - PSUBW (Parallel Subtract Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <820210309145653.743937-11-f4bug@amsat.org>
2021-07-11target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic)Philippe Mathieu-Daudé
Introduce the parallel logic opcodes: - PAND (Parallel AND) - POR (Parallel OR) - PXOR (Parallel XOR) - PNOR (Parallel NOR) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-16-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-07-09target/mips: Fix missing else in gen_goto_tbRichard Henderson
Do not emit dead code for the singlestep_enabled case, after having exited the TB with a debug exception. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/mips: Use translator_use_goto_tbRichard Henderson
Just use translator_use_goto_tb directly at the one call site, rather than maintaining a local wrapper. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé
The root trace-events only declares a single TCG event: $ git grep -w tcg trace-events trace-events:115:# tcg/tcg-op.c trace-events:137:vcpu tcg guest_mem_before(TCGv vaddr, uint16_t info) "info=%d", "vaddr=0x%016"PRIx64" info=%d" and only a tcg/tcg-op.c uses it: $ git grep -l trace_guest_mem_before_tcg tcg/tcg-op.c therefore it is pointless to include "trace-tcg.h" in each target (because it is not used). Remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210629050935.2570721-1-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09meson: Introduce target-specific KconfigPhilippe Mathieu-Daudé
Add a target-specific Kconfig. We need the definitions in Kconfig so the minikconf tool can verify they exits. However CONFIG_FOO is only enabled for target foo via the meson.build rules. Two architecture have a particularity, ARM and MIPS. As their translators have been split you can potentially build a plain 32 bit build along with a 64-bit version including the 32-bit subset. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210131111316.232778-6-f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210707131744.26027-2-alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-07-02target/mips: Extract nanoMIPS ISA translation routinesPhilippe Mathieu-Daudé
Extract 4900 lines from the huge translate.c to a new file, 'nanomips_translate.c.inc'. As there are too many inter- dependencies we don't compile it as another object, but keep including it in the big translate.o. We gain in code maintainability. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201120210844.2625602-13-f4bug@amsat.org>
2021-07-02target/mips: Extract the microMIPS ISA translation routinesPhilippe Mathieu-Daudé
Extract 3200+ lines from the huge translate.c to a new file, 'micromips_translate.c.inc'. As there are too many inter- dependencies we don't compile it as another object, but keep including it in the big translate.o. We gain in code maintainability. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201120210844.2625602-12-f4bug@amsat.org>
2021-07-02target/mips: Extract Code Compaction ASE translation routinesPhilippe Mathieu-Daudé
Extract 1100+ lines from the huge translate.c to a new file, 'mips16e_translate.c.inc'. As there are too many inter- dependencies we don't compile it as another object, but keep including it in the big translate.o. We gain in code maintainability. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201120210844.2625602-10-f4bug@amsat.org>
2021-07-02target/mips: Add declarations for generic TCG helpersPhilippe Mathieu-Daudé
We want to extract the microMIPS ISA and Code Compaction ASE to new compilation units. We will first extract this code as included source files (.c.inc), then make them new compilation units afterward. The following methods are going to be used externally: micromips_translate.c.inc:1778: gen_ldxs(ctx, rs, rt, rd); micromips_translate.c.inc:1806: gen_align(ctx, 32, rd, rs, ... micromips_translate.c.inc:2859: gen_addiupc(ctx, reg, offset, ... mips16e_translate.c.inc:444: gen_addiupc(ctx, ry, offset, ... To avoid too much code churn, it is simpler to declare these prototypes in "translate.h" now. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174907.2904067-2-f4bug@amsat.org>
2021-06-29target/mips: Fix gen_mxu_s32ldd_s32lddrRichard Henderson
There were two bugs here: (1) the required endianness was not present in the MemOp, and (2) we were not providing a zero-extended input to the bswap as semantics required. The best fix is to fold the bswap into the memory operation, producing the desired result directly. Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-29tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64Richard Henderson
Implement the new semantics in the fallback expansion. Change all callers to supply the flags that keep the semantics unchanged locally. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-24target/mips: Merge msa32/msa64 decodetree definitionsPhilippe Mathieu-Daudé
We don't need to maintain 2 sets of decodetree definitions. Merge them into a single file. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174636.2902654-3-f4bug@amsat.org>
2021-06-24target/mips: Remove pointless gen_msa()Philippe Mathieu-Daudé
Only trans_MSA() calls gen_msa(), inline it to simplify. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174636.2902654-2-f4bug@amsat.org>
2021-06-24target/mips: Optimize regnames[] arraysPhilippe Mathieu-Daudé
Since all entries are no more than 3/4/6 bytes (including nul terminator), can save space and pie runtime relocations by declaring regnames[] as array of 3/4/6 const char. Inspired-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-10-f4bug@amsat.org>
2021-06-24target/mips: Constify host_to_mips_errno[]Philippe Mathieu-Daudé
Keep host_to_mips_errno[] in .rodata by marking the array const. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-9-f4bug@amsat.org>
2021-06-24target/mips: fix emulation of nanoMIPS BPOSGE32 instructionAleksandar Rikalo
Per the "MIPS® Architecture Extension: nanoMIPS32 DSP Technical Reference Manual — Revision 0.04" p. 88 "BPOSGE32C", offset argument (imm) should be left-shifted first. This change was tested against test_dsp_r1_bposge32.c DSP test. Reported-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Filip Vidojevic <filip.vidojevic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <VI1PR0302MB34869449EE56F226FC3C21129C309@VI1PR0302MB3486.eurprd03.prod.outlook.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-06-24target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful casesPhilippe Mathieu-Daudé
These switch cases for the microMIPS BPOSGE32 / BPOSGE64 opcodes have been added commit 3c824109da0 ("target-mips: microMIPS ASE support"). More than 11 years later it is safe to assume there won't be added soon. The cases fall back to the default which generates a RESERVED INSTRUCTION, so it is safe to remove them. Functionally speaking, the patch is a no-op. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-8-f4bug@amsat.org>
2021-06-24target/mips: Remove SmartMIPS / MDMX unuseful commentsPhilippe Mathieu-Daudé
These placeholder comments for SmartMIPS and MDMX extensions have been added commit 3c824109da0 ("target-mips: microMIPS ASE support"). More than 11 years later it is safe to assume there won't be added soon, so remove these unuseful comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-7-f4bug@amsat.org>
2021-06-24target/mips: Restrict some system specific declarations to sysemuPhilippe Mathieu-Daudé
Commit 043715d1e0f ("target/mips: Update ITU to utilize SAARI and SAAR CP0 registers") declared itc_reconfigure() in public namespace, while it is restricted to system emulation. Similarly commit 5679479b9a1 ("target/mips: Move CP0 helpers to sysemu/cp0.c") restricted cpu_mips_soft_irq() definition to system emulation, but forgot to restrict its declaration. To avoid polluting user-mode emulation with these declarations, restrict them to sysemu. Also restrict the sysemu ITU/ITC/IRQ fields from CPUMIPSState. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-6-f4bug@amsat.org>
2021-06-24target/mips: Move translate.h to tcg/ sub directoryPhilippe Mathieu-Daudé
We moved various TCG source files in commit a2b0a27d33e ("target/mips: Move TCG source files under tcg/ sub directory") but forgot to move the header declaring their prototypes. Do it now, since all it declares is TCG specific. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-5-f4bug@amsat.org>
2021-06-24target/mips: Move TCG trace events to tcg/ sub directoryPhilippe Mathieu-Daudé
Commit a2b0a27d33e ("target/mips: Move TCG source files under tcg/ sub directory") forgot to move the trace-event file. As it only contains TCG events, move it for consistency. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-4-f4bug@amsat.org>
2021-06-24target/mips: Do not abort on invalid instructionPhilippe Mathieu-Daudé
On real hardware an invalid instruction doesn't halt the world, but usually triggers a RESERVED INSTRUCTION exception. TCG guest code shouldn't abort QEMU anyway. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-2-f4bug@amsat.org>
2021-06-24target/mips: Raise exception when DINSV opcode used with DSP disabledPhilippe Mathieu-Daudé
Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02, Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module": If the Module/ASE is not implemented, executing such an instruction must cause a Reserved Instruction Exception. The DINSV instruction lists the following exceptions: - Reserved Instruction - DSP Disabled If the MIPS core doesn't support the DSP module, or the DSP is disabled, do not handle the '$rt = $0' case as a no-op but raise the proper exception instead. Cc: Jia Liu <proljc@gmail.com> Fixes: 1cb6686cf92 ("target-mips: Add ASE DSP bit/manipulation instructions") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210529165443.1114402-1-f4bug@amsat.org>
2021-06-24target/mips: Fix more TCG temporary leaks in gen_pool32a5_nanomips_insnPhilippe Mathieu-Daudé
Fix multiple TCG temporary leaks in gen_pool32a5_nanomips_insn(). Fixes: 3285a3e4445 ("target/mips: Add emulation of DSP ASE for nanoMIPS - part 1") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-3-f4bug@amsat.org>
2021-06-24target/mips: Fix TCG temporary leaks in gen_pool32a5_nanomips_insn()Philippe Mathieu-Daudé
Fix a pair of TCG temporary leak when translating nanoMIPS SHILO opcode. Fixes: 3285a3e4445 ("target/mips: Add emulation of DSP ASE for nanoMIPS") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210530094538.1275329-1-f4bug@amsat.org>
2021-06-24target/mips: Fix potential integer overflow (CID 1452921)Philippe Mathieu-Daudé
Use the BIT_ULL() macro to ensure we use 64-bit arithmetic. This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN): CID 1452921: Integer handling issues: Potentially overflowing expression "1 << w" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). Fixes: 074cfcb4dae ("target/mips: Implement hardware page table walker") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210505215119.1517465-1-f4bug@amsat.org>
2021-06-05target/mips: Fix 'Uncoditional' typoPhilippe Mathieu-Daudé
Fix Uncoditional -> Unconditional typo. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Message-Id: <20210602170759.2500248-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-06-02docs: fix references to docs/devel/tracing.rstStefano Garzarella
Commit e50caf4a5c ("tracing: convert documentation to rST") converted docs/devel/tracing.txt to docs/devel/tracing.rst. We still have several references to the old file, so let's fix them with the following command: sed -i s/tracing.txt/tracing.rst/ $(git grep -l docs/devel/tracing.txt) Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210517151702.109066-2-sgarzare@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-05-26hw/core: Constify TCGCPUOpsRichard Henderson
We no longer have any runtime modifications to this struct, so declare them all const. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20210227232519.222663-3-richard.henderson@linaro.org>
2021-05-26target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failedRichard Henderson
Add a flag to MIPSCPUClass in order to avoid needing to replace mips_tcg_ops.do_transaction_failed. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20210227232519.222663-2-richard.henderson@linaro.org>
2021-05-26cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-21-f4bug@amsat.org> [rth: Drop declaration movement from target/*/cpu.h] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-16 18:57:20 +0000