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2020-11-09target/mips: Fix PageMask with variable page sizeJiaxun Yang
Our current code assumed the target page size is always 4k when handling PageMask and VPN2, however, variable page size was just added to mips target and that's no longer true. Fixes: ee3863b9d414 ("target/mips: Support variable page size") Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Message-Id: <1604636510-8347-2-git-send-email-chenhc@lemote.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Replaced find_first_zero_bit() by cto32()] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-11-03target/mips: Add unaligned access support for MIPS64R6 and Loongson-3Huacai Chen
MIPSR6 (not only MIPS32R6) processors support unaligned access in hardware, so set MO_UNALN in their default_tcg_memop_mask. Btw, new Loongson-3 (such as Loongson-3A4000) also support unaligned access, since both old and new Loongson-3 use the same binaries, we can simply set MO_UNALN for all Loongson-3 processors. Signed-off-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1604053541-27822-3-git-send-email-chenhc@lemote.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-11-03target/mips: Fix Lesser GPL version numberChetan Pant
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20201016143509.26692-1-chetan4windows@gmail.com> [PMD: Split hw/ vs target/] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-10-17target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)Philippe Mathieu-Daudé
Per "MIPS32 34K Processor Core Family Software User's Manual, Revision 01.13" page 8 in "Joint TLB (JTLB)" section: "The JTLB is a fully associative TLB cache containing 16, 32, or 64-dual-entries mapping up to 128 virtual pages to their corresponding physical addresses." There is no particular reason to restrict the 34Kf core model to 16 TLB entries, so raise its config to 64. This is helpful for other projects, in particular the Yocto Project: Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit MIPS CI loop. It was observed that in this case CI test execution time was almost twice longer than 64bit MIPS variant that runs under MIPS64R2-generic model. It was investigated and concluded that the difference in number of TLBs 16 in 34Kf case vs 64 in MIPS64R2-generic is responsible for most of CI real time execution difference. Because with 16 TLBs linux user-land trashes TLB more and it needs to execute more instructions in TLB refill handler calls, as result it runs much longer. (https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html) Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992 Reported-by: Victor Kamensky <kamensky@cisco.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201016133317.553068-1-f4bug@amsat.org>
2020-10-17target/mips/cpu: Display warning when CPU is used without input clockPhilippe Mathieu-Daudé
All our QOM users provides an input clock. In order to avoid avoid future machines added without clock, display a warning. User-mode emulation use the CP0 timer with the RDHWR instruction (see commit cdfcad788394) so keep using the fixed 200 MHz clock without diplaying any warning. Only display it in system-mode emulation. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-22-f4bug@amsat.org>
2020-10-17target/mips/cpu: Introduce mips_cpu_create_with_clock() helperPhilippe Mathieu-Daudé
Introduce an helper to create a MIPS CPU and connect it to a reference clock. This helper is not MIPS specific, but so far only MIPS CPUs need it. Suggested-by: Huacai Chen <zltjiangshi@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-13-f4bug@amsat.org>
2020-10-17target/mips/cpu: Allow the CPU to use dynamic frequenciesPhilippe Mathieu-Daudé
Use the Clock API and let the CPU object have an input clock. If no clock is connected, keep using the default frequency of 200 MHz used since the introduction of the 'r4k' machine in commit 6af0bf9c7c3. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-12-f4bug@amsat.org>
2020-10-17target/mips/cpu: Make cp0_count_rate a propertyPhilippe Mathieu-Daudé
Since not all CPU implementations use a cores use a CP0 timer at half the frequency of the CPU, make this variable a property. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-11-f4bug@amsat.org>
2020-10-17target/mips/cpu: Calculate the CP0 timer period using the CPU frequencyPhilippe Mathieu-Daudé
The CP0 timer period is a function of the CPU frequency. Start using the default values, which will be replaced by properties in the next commits. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201012095804.3335117-10-f4bug@amsat.org>
2020-10-17target/mips: Move cp0_count_ns to CPUMIPSStatePhilippe Mathieu-Daudé
Currently the CP0 timer period is fixed at 10 ns, corresponding to a fixed CPU frequency of 200 MHz (using half the speed of the CPU). In few commits we will be able to use a different CPU frequency. In preparation, move the cp0_count_ns variable to CPUMIPSState so we can modify it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201012095804.3335117-9-f4bug@amsat.org>
2020-10-17target/mips/cp0_timer: Document TIMER_PERIOD originPhilippe Mathieu-Daudé
TIMER_PERIOD value of '10 ns' can be explained looking at commit 6af0bf9c7c3doc, where the CPU frequency is 200 MHz and CP0 default count rate is half the frequency of the CPU. Document that. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-8-f4bug@amsat.org>
2020-10-17target/mips/cp0_timer: Explicit unit in variable namePhilippe Mathieu-Daudé
Name variables holding nanoseconds with the '_ns' suffix. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20201012095804.3335117-7-f4bug@amsat.org>
2020-10-17target/mips: Move cpu_mips_get_random() with CP0 helpersPhilippe Mathieu-Daudé
The get_random() helper uses the CP0_Wired register, which is unrelated to the CP0_Count register used as timer. Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file") incorrectly moved this get_random() helper with timer specific code. Move it back to generic CP0 helpers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-Id: <20201012095804.3335117-6-f4bug@amsat.org>
2020-10-17target/mips/op_helper: Log unimplemented cache opcodePhilippe Mathieu-Daudé
In case the guest uses a cache opcode we are not expecting, log it to give us a chance to notice it, in case we should actually do something. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20200813181527.22551-4-f4bug@amsat.org>
2020-10-17target/mips/op_helper: Document Invalidate/Writeback opcodes as no-opPhilippe Mathieu-Daudé
QEMU does not model caches, so there is not much to do with the Invalidate/Writeback opcodes. Make it explicit adding a comment. Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20200813181527.22551-3-f4bug@amsat.org>
2020-10-17target/mips/op_helper: Convert multiple if() to switch casePhilippe Mathieu-Daudé
The cache operation is encoded in bits [20:18] of the instruction. The 'op' argument of helper_cache() contains the bits [20:16]. Extract the 3 bits and parse them using a switch case. This allow us to handle multiple cache types (the cache type is encoded in bits [17:16]). Previously the if() block was only checking the D-Cache (Primary Data or Unified Primary). Now we also handle the I-Cache (Primary Instruction), S-Cache (Secondary) and T-Cache (Terciary). Reported-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20200813181527.22551-2-f4bug@amsat.org>
2020-10-17target/mips: Add loongson-ext lsdc2 group of instructionsJiaxun Yang
LDC2/SDC2 opcodes have been rewritten as "load & store with offset" group of instructions by loongson-ext ASE. This patch add implementation of these instructions: gslbx: load 1 bytes to GPR gslhx: load 2 bytes to GPR gslwx: load 4 bytes to GPR gsldx: load 8 bytes to GPR gslwxc1: load 4 bytes to FPR gsldxc1: load 8 bytes to FPR gssbx: store 1 bytes from GPR gsshx: store 2 bytes from GPR gsswx: store 4 bytes from GPR gssdx: store 8 bytes from GPR gsswxc1: store 4 bytes from FPR gssdxc1: store 8 bytes from FPR Details of Loongson-EXT is here: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1602831120-3377-5-git-send-email-chenhc@lemote.com>
2020-10-17target/mips: Add loongson-ext lswc2 group of instructions (Part 2)Jiaxun Yang
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE as "load/store quad word" and "shifted load/store" groups of instructions. This patch add implementation of these instructions: gslwlc1: similar to lwl but RT is FPR instead of GPR gslwrc1: similar to lwr but RT is FPR instead of GPR gsldlc1: similar to ldl but RT is FPR instead of GPR gsldrc1: similar to ldr but RT is FPR instead of GPR gsswlc1: similar to swl but RT is FPR instead of GPR gsswrc1: similar to swr but RT is FPR instead of GPR gssdlc1: similar to sdl but RT is FPR instead of GPR gssdrc1: similar to sdr but RT is FPR instead of GPR Details of Loongson-EXT is here: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Message-Id: <1602831120-3377-4-git-send-email-chenhc@lemote.com> [PMD: Reuse t1 on MIPS32, reintroduce t2/fp0] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-10-17target/mips: Add loongson-ext lswc2 group of instructions (Part 1)Jiaxun Yang
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE as "load/store quad word" and "shifted load/store" groups of instructions. This patch add implementation of these instructions: gslq: load 16 bytes to GPR gssq: store 16 bytes from GPR gslqc1: load 16 bytes to FPR gssqc1: store 16 bytes from FPR Details of Loongson-EXT is here: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Message-Id: <1602831120-3377-3-git-send-email-chenhc@lemote.com> [PMD: Restrict t1 variable to TARGET_MIPS64, remove unused t2/fp0] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-10-17target/mips: Demacro helpers for <MAX|MAXA|MIN|MINA>.<D|S>Aleksandar Markovic
Remove function definitions via macros to achieve better code clarity. Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1602103041-32017-4-git-send-email-aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-10-17target/mips: Demacro helpers for M<ADD|SUB>F.<D|S>Aleksandar Markovic
Remove function definitions via macros to achieve better code clarity. Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1602103041-32017-3-git-send-email-aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-10-17target/mips: Demacro helpers for <ABS|CHS>.<D|S|PS>Aleksandar Markovic
Remove function definitions via macros to achieve better code clarity. Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1602103041-32017-2-git-send-email-aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-10-17target/mips: Fix some comment spelling errorszhaolichang
There are many spelling errors in the comments in target/mips/. Use spellcheck to check the spelling errors. Signed-off-by: zhaolichang <zhaolichang@huawei.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201009064449.2336-7-zhaolichang@huawei.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-09-18qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost
One of the goals of having less boilerplate on QOM declarations is to avoid human error. Requiring an extra argument that is never used is an opportunity for mistakes. Remove the unused argument from OBJECT_DECLARE_TYPE and OBJECT_DECLARE_SIMPLE_TYPE. Coccinelle patch used to convert all users of the macros: @@ declarer name OBJECT_DECLARE_TYPE; identifier InstanceType, ClassType, lowercase, UPPERCASE; @@ OBJECT_DECLARE_TYPE(InstanceType, ClassType, - lowercase, UPPERCASE); @@ declarer name OBJECT_DECLARE_SIMPLE_TYPE; identifier InstanceType, lowercase, UPPERCASE; @@ OBJECT_DECLARE_SIMPLE_TYPE(InstanceType, - lowercase, UPPERCASE); Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: Cornelia Huck <cohuck@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20200916182519.415636-4-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-12Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-testing-fixes-100920-1' into staging Various misc and testing fixes: - Expand CODING_STYLE.rst a little more - usb-host build fix - allow check-softfloat unit tests without TCG - simplify mips imm_branch so compiler isn't confused - mark ppc64abi32 for deprecation - more compiler soothing in pch_rev_id - allow acceptance to skip missing binaries - more a bunch of plugins to contrib # gpg: Signature made Thu 10 Sep 2020 10:51:05 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-fixes-100920-1: plugins: move the more involved plugins to contrib tests/acceptance: Add Test.fetch_asset(cancel_on_missing=True) tests: bump avocado version hw/i386: make explicit clearing of pch_rev_id configure: don't enable ppc64abi32-linux-user by default docs/system/deprecated: mark ppc64abi32-linux-user for deprecation target/mips: simplify gen_compute_imm_branch logic tests/meson.build: fp tests don't need CONFIG_TCG usb-host: restrict workaround to new libusb versions CODING_STYLE.rst: flesh out our naming conventions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-10target/mips: simplify gen_compute_imm_branch logicAlex Bennée
One of the Travis builds was complaining about: qemu/include/tcg/tcg.h:437:12: error: ‘cond’ may be used uninitialized in this function [-Werror=maybe-uninitialized] return (TCGCond)(c ^ 1); ../target/mips/translate.c:20031:13: note: ‘cond’ was declared here TCGCond cond; Rather than figure out exactly which one was causing the complaint I just defaulted to TCG_COND_ALWAYS and allowed that state to double up for the now defunct bcond_compute variable. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200909112742.25730-5-alex.bennee@linaro.org>
2020-09-09Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost
Replace DECLARE_OBJ_CHECKERS with OBJECT_DECLARE_TYPE where the typedefs can be safely removed. Generated running: $ ./scripts/codeconverter/converter.py -i \ --pattern=DeclareObjCheckers $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20200831210740.126168-16-ehabkost@redhat.com> Message-Id: <20200831210740.126168-17-ehabkost@redhat.com> Message-Id: <20200831210740.126168-18-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost
Generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-13-ehabkost@redhat.com> Message-Id: <20200831210740.126168-14-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost
Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE. Patch generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]') which will split "typdef struct { ... } TypedefName" declarations. Followed by: $ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \ $(git grep -l '' -- '*.[ch]') which will: - move the typedefs and #defines above the type check macros - add missing #include "qom/object.h" lines if necessary Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-9-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-10-ehabkost@redhat.com> Message-Id: <20200831210740.126168-11-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-21meson: targetPaolo Bonzini
Similar to hw_arch, each architecture defines two sourceset which are placed in dictionaries target_arch and target_softmmu_arch. These are then picked up from there when building the per-emulator static_library. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini
With Makefiles that have automatically generated dependencies, you generated includes are set as dependencies of the Makefile, so that they are built before everything else and they are available when first building the .c files. Alternatively you can use a fine-grained dependency, e.g. target/arm/translate.o: target/arm/decode-neon-shared.inc.c With Meson you have only one choice and it is a third option, namely "build at the beginning of the corresponding target"; the way you express it is to list the includes in the sources of that target. The problem is that Meson decides if something is a source vs. a generated include by looking at the extension: '.c', '.cc', '.m', '.C' are sources, while everything else is considered an include---including '.inc.c'. Use '.c.inc' to avoid this, as it is consistent with our other convention of using '.rst.inc' for included reStructuredText files. The editorconfig file is adjusted. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-08-21trace: switch position of headers to what Meson requiresPaolo Bonzini
Meson doesn't enjoy the same flexibility we have with Make in choosing the include path. In particular the tracing headers are using $(build_root)/$(<D). In order to keep the include directives unchanged, the simplest solution is to generate headers with patterns like "trace/trace-audio.h" and place forwarding headers in the source tree such that for example "audio/trace.h" includes "trace/trace-audio.h". This patch is too ugly to be applied to the Makefiles now. It's only a way to separate the changes to the tracing header files from the Meson rewrite of the tracing logic. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-07-14target/mips: Fix ADD.S FPU instructionAlex Richardson
After merging latest QEMU upstream into our CHERI fork, I noticed that some of the FPU tests in our MIPS baremetal testsuite [*] started failing. It turns out commit 1ace099f2a accidentally changed add.s into a subtract. [*] https://github.com/CTSRD-CHERI/cheritest Fixes: 1ace099f2a ("target/mips: fpu: Demacro ADD.<D|S|PS>") Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200703161515.25966-1-Alexander.Richardson@cl.cam.ac.uk> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-07-14target/mips: Remove identical if/else branchesAleksandar Markovic
Remove the segment: if (other_tc == other->current_tc) { tccause = other->CP0_Cause; } else { tccause = other->CP0_Cause; } Original contributor can't remember what was his intention. Fixes: 5a25ce9487 ("mips: Hook in more reg accesses via mttr/mftr") Buglink: https://bugs.launchpad.net/qemu/+bug/1885718 Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200701182559.28841-2-aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-06-27hw/mips: Implement the kvm_type() hook in MachineClassHuacai Chen
MIPS has two types of KVM: TE & VZ, and TE is the default type. Now we can't create a VZ guest in QEMU because it lacks the kvm_type() hook in MachineClass. This patch add the the kvm_type() hook to support both of the two types. [AM: Added "if defined" guards.] Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <1592995531-32600-2-git-send-email-chenhc@lemote.com>
2020-06-15target/mips: msa: Split helpers for MULV.<B|H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-15-aleksandar.qemu.devel@gmail.com>
2020-06-15target/mips: msa: Split helpers for SUBV.<B|H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-14-aleksandar.qemu.devel@gmail.com>
2020-06-15target/mips: msa: Split helpers for SUBSUU_S.<B|H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-13-aleksandar.qemu.devel@gmail.com>
2020-06-15target/mips: msa: Split helpers for SUBSUS_U.<B|H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-12-aleksandar.qemu.devel@gmail.com>
2020-06-15target/mips: msa: Split helpers for SUBS_U.<B|H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-11-aleksandar.qemu.devel@gmail.com>
2020-06-15target/mips: msa: Split helpers for SUBS_S.<B|H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-10-aleksandar.qemu.devel@gmail.com>
2020-06-15target/mips: msa: Split helpers for DOTP_U.<H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-9-aleksandar.qemu.devel@gmail.com>
2020-06-15target/mips: msa: Split helpers for DOTP_S.<H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-8-aleksandar.qemu.devel@gmail.com>
2020-06-15target/mips: msa: Split helpers for DPSUB_U.<H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-7-aleksandar.qemu.devel@gmail.com>
2020-06-15target/mips: msa: Split helpers for DPSUB_S.<H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-6-aleksandar.qemu.devel@gmail.com>
2020-06-15target/mips: msa: Split helpers for DPADD_U.<H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-5-aleksandar.qemu.devel@gmail.com>
2020-06-15target/mips: msa: Split helpers for DPADD_S.<H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-4-aleksandar.qemu.devel@gmail.com>
2020-06-15target/mips: msa: Split helpers for MSUBV.<B|H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-3-aleksandar.qemu.devel@gmail.com>
2020-06-15target/mips: msa: Split helpers for MADDV.<B|H|W|D>Aleksandar Markovic
Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200613152133.8964-2-aleksandar.qemu.devel@gmail.com>
2020-06-15target/mips: Add comments for vendor-specific ASEsJiaxun Yang
Abbreviations of vendor-specific ASEs looks very similiar. Add comments to explain the full name and vendors of these flags. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200614080049.31134-3-jiaxun.yang@flygoat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-07 13:02:36 +0000