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2023-08-22mips: Report an error when KVM_VM_MIPS_VZ is unavailableAkihiko Odaki
On MIPS, QEMU requires KVM_VM_MIPS_VZ type for KVM. Report an error in such a case as other architectures do when an error occurred during KVM type decision. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-id: 20230727073134.134102-4-akihiko.odaki@daynix.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-08-22kvm: Introduce kvm_arch_get_default_type hookAkihiko Odaki
kvm_arch_get_default_type() returns the default KVM type. This hook is particularly useful to derive a KVM type that is valid for "none" machine model, which is used by libvirt to probe the availability of KVM. For MIPS, the existing mips_kvm_type() is reused. This function ensures the availability of VZ which is mandatory to use KVM on the current QEMU. Cc: qemu-stable@nongnu.org Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-id: 20230727073134.134102-2-akihiko.odaki@daynix.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added doc comment for new function] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-25target/mips: Avoid shift by negative number in page_table_walk_refill()Peter Maydell
Coverity points out that in page_table_walk_refill() we can shift by a negative number, which is undefined behaviour (CID 1452918, 1452920, 1452922). We already catch the negative directory_shift and leaf_shift as being a "bail out early" case, but not until we've already used them to calculated some offset values. The shifts can be negative only if ptew > 1, so make the bail-out-early check look directly at that, and only calculate the shift amounts and the offsets based on them after we have done that check. This allows us to simplify the expressions used to calculate the shift amounts, use an unsigned type, and avoids the undefined behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> [PMD: Check for ptew > 1, use unsigned type] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20230717213504.24777-3-philmd@linaro.org>
2023-07-25target/mips: Pass directory/leaf shift values to walk_directory()Philippe Mathieu-Daudé
We already evaluated directory_shift and leaf_shift in page_table_walk_refill(), no need to do that again: pass as argument. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20230717213504.24777-2-philmd@linaro.org>
2023-07-25target/mips/mxu: Avoid overrun in gen_mxu_q8adde()Philippe Mathieu-Daudé
Coverity reports a potential overruns (CID 1517770): Overrunning array "mxu_gpr" of 15 8-byte elements at element index 4294967295 (byte offset 34359738367) using index "XRb - 1U" (which evaluates to 4294967295). Add a gen_extract_mxu_gpr() helper similar to gen_load_mxu_gpr() to safely extract MXU registers. Fixes: eb79951ab6 ("target/mips/mxu: Add Q8ADDE ... insns") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230712060806.82323-4-philmd@linaro.org>
2023-07-25target/mips/mxu: Avoid overrun in gen_mxu_S32SLT()Philippe Mathieu-Daudé
Coverity reports a potential overrun (CID 1517769): Overrunning array "mxu_gpr" of 15 8-byte elements at element index 4294967295 (byte offset 34359738367) using index "XRb - 1U" (which evaluates to 4294967295). Use gen_load_mxu_gpr() to safely load MXU registers. Fixes: ff7936f009 ("target/mips/mxu: Add S32SLT ... insns") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230712060806.82323-3-philmd@linaro.org>
2023-07-25target/mips/mxu: Replace magic array size by its definitionPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230712060806.82323-2-philmd@linaro.org>
2023-07-10target/mips: enable GINVx support for I6400 and I6500Marcin Nowakowski
GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores, so indicate that properly in CP0.Config5 register bits [16:15]. Cc: qemu-stable@nongnu.org Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230630072806.3093704-1-marcin.nowakowski@fungible.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q8SAD instructionSiarhei Volkau
The instruction implements SAD (sum-absolute-difference) operation which is used in motion estimation algorithms. The instruction handles four 8-bit data in parallel. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-34-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S32SFL instructionSiarhei Volkau
The instruction shuffles 8 bytes in two registers by one of 4 predefined patterns. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-33-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q8MADL instructionSiarhei Volkau
The instruction is used to parallel multiply and accumulate four 8-bit data. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-32-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q16SCOP instructionSiarhei Volkau
The instruction is used to determine sign of four 16-bit packed data in parallel. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-31-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q8MAC Q8MACSU instructionsSiarhei Volkau
These instructions do parallel quad 8-bit multiply and accumulate. They are close to existing Q8MUL Q8MULSU so the generation function modified to support all of them. Also the patch fixes decoding of Q8MULSU according to tests on hardware. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-30-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructionsSiarhei Volkau
These instructions are: - single 32-bit - dual 16-bit packed - quad 8-bit packed conditional moves. They are grouped in pool20 in the source code. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-29-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D32/Q16- SLLV/SLRV/SARV instructionsSiarhei Volkau
These instructions are counterparts for D32/Q16-SLL/SLR/SAR with difference that the shift amount placed into GPR. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-28-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q16SLL Q16SLR Q16SAR instructionsSiarhei Volkau
These instructions are same data shift in various directions, thus one generation function is implemented for all three. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-27-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D32SLL D32SLR D32SAR instructionsSiarhei Volkau
These instructions are same data shift in various directions, thus one generation function is implemented for all three. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-26-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D32SARL D32SARW instructionsSiarhei Volkau
These instructions are dual 32-bit arithmetic shift right and pack LSBs to 2x 16-bit into a MXU register. The difference is the shift amount source: immediate or GP reg. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-25-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S32ALN S32LUI insnsSiarhei Volkau
These instructions are part of pool16, see the grand opcode organization tree on top of the file. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-24-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insnsSiarhei Volkau
These instructions are part of pool15, see the grand opcode organization tree on top of the file. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-23-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S16LDD S16STD S16LDI S16SDI instructionsSiarhei Volkau
These instructions are all load/store a halfword from memory and put it into/get it from MXU register in various combinations. I-suffix instructions modify the base address GPR by offset provided. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-22-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S8STD S8LDI S8SDI instructionsSiarhei Volkau
These instructions are all load/store a byte from memory and put it into/get it from MXU register in various combinations. I-suffix instructions modify the base address GPR by offset provided. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-21-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q8ADDE Q8ACCE D8SUM D8SUMC instructionsSiarhei Volkau
These instructions are all dual 8-bit addition/subtraction in various combinations. Most instructions are grouped in pool14, see the opcode organization in the file. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-20-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q16ACC Q16ACCM D16ASUM instructionsSiarhei Volkau
These instructions are all dual 16-bit addition/subtraction in various combinations. The instructions are grouped in pool13, see the opcode organization in the file. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-19-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D32ADDC instructionSiarhei Volkau
The instruction adds two 32-bit values with respect to corresponding carry flags in MXU_CR. XRa += XRb + LeftCarry flag; XRd += XRc + RightCarry flag; Suddenly, it doesn't modify carry flags as a result of addition. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-18-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D32ACC D32ACCM D32ASUM instructionsSiarhei Volkau
These instructions are all dual 32-bit addition/subtraction in various combinations. The instructions are grouped in pool12, see the opcode organization in the file. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-17-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D32ADD instructionSiarhei Volkau
The instruction adds/subtracts two 32-bit values in XRb and XRc. Placing results in XRa and XRd and updates carry bits for each path in the MXU control register. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-16-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q16ADD instructionSiarhei Volkau
The instruction adds/subtracts four 16-bit packed in XRb and XRc. Placing packed 16-bit results in XRa and XRd. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-15-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S16MAD instructionSiarhei Volkau
The instruction is similar to multiply and accumulate but works with MXU registers set. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-14-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D16MADL instructionSiarhei Volkau
The instruction is similar to multiply and accumulate but works with MXU registers set. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-13-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D16MACF D16MACE instructionsSiarhei Volkau
These instructions are close to D16MAC so common generation function provided. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-12-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D16MULF D16MULE instructionsSiarhei Volkau
These instructions are part of pool3, see the grand tree above in the file. The instructions are close to D16MUL so common generation function provided. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-11-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S32CPS D16CPS Q8ABD Q16SAT insnsSiarhei Volkau
These instructions are part of pool2, see the grand tree above in the file. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-10-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q8ADD instructionSiarhei Volkau
This instruction is used to add/subtract quadruple 8-bit values to another quadruple in parallel. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-9-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S32SLT D16SLT D16AVG[R] Q8AVG[R] insnsSiarhei Volkau
These instructions are part of pool1, see the grand tree above in the file. Q8ADD is part of pool1 too but belong to another category of instructions, thus will be made in later patches. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-8-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Fix D16MAX D16MIN Q8MAX Q8MIN instructionsSiarhei Volkau
These instructions were designed that they overwrite source register during partial storing of result. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-7-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q8SLT Q8SLTU instructionsSiarhei Volkau
These instructions are used to set bits depending on comparison result in each byte respectively. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-6-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S32MADD/MADDU/MSUB/MSUBU instructionsSiarhei Volkau
These instructions used to multiply 2x32-bit GPR sources & accumulate result into 64-bit pair of XRF registers. These instructions stain HI/LO registers with the final result. Their opcode is close to the MIPS32R1 MADD[U]/MSUB[U], so it have to call decode_opc_special2_legacy when failing to find MXU opcode. Moreover, it solves issue with reinventing MUL and malfunction MULU/CLZ/CLO instructions. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-5-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add LXW LXB LXH LXBU LXHU instructionsSiarhei Volkau
These instructions used to load from memory to GPR via indexed address divided by base and index parts in GPR registers. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-4-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips: Add support of two XBurst CPUsSiarhei Volkau
XBurstR1 - is the MIPS32R1 CPU which aims to cover all Ingenic SoCs older than JZ4770 and some newer. XBurstR2 - is the MIPS32R2 CPU which aims to cover all Ingenic SoCs starting from to JZ4770. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-3-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips: Add emulation of MXU instructions for 32-bit load/storeSiarhei Volkau
Add support for emulating: - S32LDDV and S32LDDVR - S32STD and S32STDR - S32STDV and S32STDVR MXU instructions. Add support for emulating MXU instructions with address register post-modify counterparts: - S32LDI and S32LDIR - S32LDIV and S32LDIVR - S32SDI and S32SDIR - S32SDIV and S32SDIVR Refactor support for emulating the S32LDD and S32LDDR instructions. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-2-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips: Implement Loongson CSR instructionsJiaxun Yang
Loongson introduced CSR instructions since 3A4000, which looks similar to IOCSR and CPUCFG instructions we seen in LoongArch. Unfortunately we don't have much document about those instructions, bit fields of CPUCFG instructions and IOCSR registers can be found at 3A4000's user manual, while instruction encodings can be found at arch/mips/include/asm/mach-loongson64/loongson_regs.h from Linux Kernel. Our predefined CPUCFG bits are differ from actual 3A4000, since we can't emulate all CPUCFG features present in 3A4000 for now, we just enable bits for what we have in TCG. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20230521214832.20145-2-jiaxun.yang@flygoat.com> [JY: Fixed typo in ase_lcsr_available(), retrict GEN_FALSE_TRANS] [PMD: Fix meson's mips_softmmu_ss -> mips_system_ss, restrict AddressSpace/MemoryRegion to SysEmu] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips: Rework cp0_timer with clock APIJiaxun Yang
Previous implementation of MIPS cp0_timer computes a cp0_count_ns based on input clock. However rounding error of cp0_count_ns can affect precision of cp0_timer. Using clock API and a divider for cp0_timer, so we can use clock_ns_to_ticks/clock_ns_to_ticks to avoid rounding issue. Also workaround the situation that in such handler flow: count = read_c0_count() write_c0_compare(count) If timer had not progressed when compare was written, the interrupt would trigger again. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230521110037.90049-1-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-06-26target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson
Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230621135633.1649-4-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-20meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé
We use the user_ss[] array to hold the user emulation sources, and the softmmu_ss[] array to hold the system emulation ones. Hold the latter in the 'system_ss[]' array for parity with user emulation. Mechanical change doing: $ sed -i -e s/softmmu_ss/system_ss/g $(git grep -l softmmu_ss) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-10-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05target/*: Add missing includes of exec/translation-block.hRichard Henderson
This had been pulled in via exec/exec-all.h, via exec/translator.h, but the include of exec-all.h will be removed. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05target/mips: Tidy helpers for translationRichard Henderson
Move most includes from *translate*.c to translate.h, ensuring that we get the ordering correct. Ensure cpu.h is first. Use disas/disas.h instead of exec/log.h. Drop otherwise unused includes. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson
New wrapper around gen_io_start which takes care of the USE_ICOUNT check, as well as marking the DisasContext to end the TB. Remove exec/gen-icount.h. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson
In preparation for compiling tcg/ only once, eliminate the all_helpers array. Instantiate the info structs for the generic helpers in accel/tcg/, and the structs for the target-specific helpers in each translate.c. Since we don't see all of the info structs at startup, initialize at first use, using g_once_init_* to make sure we don't race while doing so. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05tcg: Move TCGv, dup_const_tl definitions to tcg-op.hRichard Henderson
These two items are the last uses of TARGET_LONG_BITS within tcg.h, and are more in common with the other "_tl" definitions within that file. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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