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AgeCommit message (Expand)Author
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster
2019-04-18target: Simplify how the TARGET_cpu_list() printMarkus Armbruster
2019-03-22trace-events: Shorten file names in commentsMarkus Armbruster
2019-02-27target/mips: Preparing for adding MMI instructionsMateja Marjanovic
2019-02-21target/mips: implement QMP query-cpu-definitions commandPavel Dovgalyuk
2019-02-14target/mips: introduce MTTCG-enabled buildsAleksandar Markovic
2019-02-14target/mips: hold BQL in mips_vpe_wake()Goran Ferenc
2019-02-14hw/mips_int: hold BQL for all interrupt requestsAleksandar Markovic
2019-02-14target/mips: reimplement SC instruction emulation and use cmpxchgLeon Alrae
2019-02-14target/mips: compare virtual addresses in LL/SC sequenceLeon Alrae
2019-01-24target/mips: Add I6500 core configurationYongbok Kim
2019-01-24target/mips: nanoMIPS: Fix branch handlingStefan Markovic
2019-01-24target/mips: Extend gen_scwp() functionality to support EVAAleksandar Markovic
2019-01-24target/mips: Correct the second argument type of cpu_supports_isa()Aleksandar Markovic
2019-01-24target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbersAleksandar Markovic
2019-01-24target/mips: nanoMIPS: Remove an unused macroAleksandar Markovic
2019-01-24target/mips: nanoMIPS: Remove duplicate macro definitionsAleksandar Markovic
2019-01-18target/mips: Introduce 32 R5900 multimedia registersFredrik Noring
2019-01-18target/mips: Rename 'rn' to 'register_name'Aleksandar Markovic
2019-01-18target/mips: Add CP0 register MemoryMapIDAleksandar Markovic
2019-01-18target/mips: Amend preprocessor constants for CP0 registersAleksandar Markovic
2019-01-18target/mips: Update ITU to utilize SAARI and SAAR CP0 registersYongbok Kim
2019-01-18target/mips: Provide R/W access to SAARI and SAAR CP0 registersYongbok Kim
2019-01-18target/mips: Add fields for SAARI and SAAR CP0 registersYongbok Kim
2019-01-18target/mips: Use preprocessor constants for 32 major CP0 registersAleksandar Markovic
2019-01-18target/mips: Add preprocessor constants for 32 major CP0 registersAleksandar Markovic
2019-01-18target/mips: Move comment containing summary of CP0 registersAleksandar Markovic
2019-01-11avoid TABs in files that only contain a fewPaolo Bonzini
2019-01-03target/mips: Support R5900 three-operand MADD1 and MADDU1 instructionsFredrik Noring
2019-01-03target/mips: Support R5900 three-operand MADD and MADDU instructionsPhilippe Mathieu-Daudé
2019-01-03target/mips: MXU: Add handler for an align instructionAleksandar Markovic
2019-01-03target/mips: MXU: Add handlers for max/min instructionsAleksandar Markovic
2019-01-03target/mips: MXU: Add handlers for logic instructionsAleksandar Markovic
2019-01-03target/mips: MXU: Improve the comment containing MXU overviewAleksandar Markovic
2019-01-03target/mips: MXU: Add generic naming for optn2 constantsAleksandar Markovic
2019-01-03target/mips: MXU: Add missing opcodes/decoding for LX* instructionsAleksandar Markovic
2018-11-27vmstate: constify VMStateFieldMarc-André Lureau
2018-11-17target/mips: Disable R5900 supportAleksandar Markovic
2018-11-17target/mips: Rename MMI-related functionsAleksandar Markovic
2018-11-17target/mips: Rename MMI-related opcodesAleksandar Markovic
2018-11-17target/mips: Rename MMI-related masksAleksandar Markovic
2018-11-17target/mips: Guard check_insn with INSN_R5900 checkFredrik Noring
2018-11-17target/mips: Guard check_insn_opc_user_only with INSN_R5900 checkFredrik Noring
2018-11-17target/mips: Fix decoding mechanism of special R5900 opcodesFredrik Noring
2018-11-17target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1Fredrik Noring
2018-11-17target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1Fredrik Noring
2018-10-29target/mips: Amend MXU ASE overview noteAleksandar Markovic
2018-10-29target/mips: Move MXU_EN check one level higherAleksandar Markovic
2018-10-29target/mips: Add emulation of MXU instructions S32LDD and S32LDDRCraig Janeczek