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QEMU is a generic and open source machine & userspace emulator and virtualizer
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2019-04-24
tcg: Hoist max_insns computation to tb_gen_code
Richard Henderson
2019-04-18
qom/cpu: Simplify how CPUClass:cpu_dump_state() prints
Markus Armbruster
2019-04-18
target: Simplify how the TARGET_cpu_list() print
Markus Armbruster
2019-03-22
trace-events: Shorten file names in comments
Markus Armbruster
2019-02-27
target/mips: Preparing for adding MMI instructions
Mateja Marjanovic
2019-02-21
target/mips: implement QMP query-cpu-definitions command
Pavel Dovgalyuk
2019-02-14
target/mips: introduce MTTCG-enabled builds
Aleksandar Markovic
2019-02-14
target/mips: hold BQL in mips_vpe_wake()
Goran Ferenc
2019-02-14
hw/mips_int: hold BQL for all interrupt requests
Aleksandar Markovic
2019-02-14
target/mips: reimplement SC instruction emulation and use cmpxchg
Leon Alrae
2019-02-14
target/mips: compare virtual addresses in LL/SC sequence
Leon Alrae
2019-01-24
target/mips: Add I6500 core configuration
Yongbok Kim
2019-01-24
target/mips: nanoMIPS: Fix branch handling
Stefan Markovic
2019-01-24
target/mips: Extend gen_scwp() functionality to support EVA
Aleksandar Markovic
2019-01-24
target/mips: Correct the second argument type of cpu_supports_isa()
Aleksandar Markovic
2019-01-24
target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbers
Aleksandar Markovic
2019-01-24
target/mips: nanoMIPS: Remove an unused macro
Aleksandar Markovic
2019-01-24
target/mips: nanoMIPS: Remove duplicate macro definitions
Aleksandar Markovic
2019-01-18
target/mips: Introduce 32 R5900 multimedia registers
Fredrik Noring
2019-01-18
target/mips: Rename 'rn' to 'register_name'
Aleksandar Markovic
2019-01-18
target/mips: Add CP0 register MemoryMapID
Aleksandar Markovic
2019-01-18
target/mips: Amend preprocessor constants for CP0 registers
Aleksandar Markovic
2019-01-18
target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
Yongbok Kim
2019-01-18
target/mips: Provide R/W access to SAARI and SAAR CP0 registers
Yongbok Kim
2019-01-18
target/mips: Add fields for SAARI and SAAR CP0 registers
Yongbok Kim
2019-01-18
target/mips: Use preprocessor constants for 32 major CP0 registers
Aleksandar Markovic
2019-01-18
target/mips: Add preprocessor constants for 32 major CP0 registers
Aleksandar Markovic
2019-01-18
target/mips: Move comment containing summary of CP0 registers
Aleksandar Markovic
2019-01-11
avoid TABs in files that only contain a few
Paolo Bonzini
2019-01-03
target/mips: Support R5900 three-operand MADD1 and MADDU1 instructions
Fredrik Noring
2019-01-03
target/mips: Support R5900 three-operand MADD and MADDU instructions
Philippe Mathieu-Daudé
2019-01-03
target/mips: MXU: Add handler for an align instruction
Aleksandar Markovic
2019-01-03
target/mips: MXU: Add handlers for max/min instructions
Aleksandar Markovic
2019-01-03
target/mips: MXU: Add handlers for logic instructions
Aleksandar Markovic
2019-01-03
target/mips: MXU: Improve the comment containing MXU overview
Aleksandar Markovic
2019-01-03
target/mips: MXU: Add generic naming for optn2 constants
Aleksandar Markovic
2019-01-03
target/mips: MXU: Add missing opcodes/decoding for LX* instructions
Aleksandar Markovic
2018-11-27
vmstate: constify VMStateField
Marc-André Lureau
2018-11-17
target/mips: Disable R5900 support
Aleksandar Markovic
2018-11-17
target/mips: Rename MMI-related functions
Aleksandar Markovic
2018-11-17
target/mips: Rename MMI-related opcodes
Aleksandar Markovic
2018-11-17
target/mips: Rename MMI-related masks
Aleksandar Markovic
2018-11-17
target/mips: Guard check_insn with INSN_R5900 check
Fredrik Noring
2018-11-17
target/mips: Guard check_insn_opc_user_only with INSN_R5900 check
Fredrik Noring
2018-11-17
target/mips: Fix decoding mechanism of special R5900 opcodes
Fredrik Noring
2018-11-17
target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1
Fredrik Noring
2018-11-17
target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1
Fredrik Noring
2018-10-29
target/mips: Amend MXU ASE overview note
Aleksandar Markovic
2018-10-29
target/mips: Move MXU_EN check one level higher
Aleksandar Markovic
2018-10-29
target/mips: Add emulation of MXU instructions S32LDD and S32LDDR
Craig Janeczek
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