| Age | Commit message (Expand) | Author |
|---|
| 2018-11-27 | vmstate: constify VMStateField | Marc-André Lureau |
| 2018-11-17 | target/mips: Disable R5900 support | Aleksandar Markovic |
| 2018-11-17 | target/mips: Rename MMI-related functions | Aleksandar Markovic |
| 2018-11-17 | target/mips: Rename MMI-related opcodes | Aleksandar Markovic |
| 2018-11-17 | target/mips: Rename MMI-related masks | Aleksandar Markovic |
| 2018-11-17 | target/mips: Guard check_insn with INSN_R5900 check | Fredrik Noring |
| 2018-11-17 | target/mips: Guard check_insn_opc_user_only with INSN_R5900 check | Fredrik Noring |
| 2018-11-17 | target/mips: Fix decoding mechanism of special R5900 opcodes | Fredrik Noring |
| 2018-11-17 | target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1 | Fredrik Noring |
| 2018-11-17 | target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1 | Fredrik Noring |
| 2018-10-29 | target/mips: Amend MXU ASE overview note | Aleksandar Markovic |
| 2018-10-29 | target/mips: Move MXU_EN check one level higher | Aleksandar Markovic |
| 2018-10-29 | target/mips: Add emulation of MXU instructions S32LDD and S32LDDR | Craig Janeczek |
| 2018-10-29 | target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU | Craig Janeczek |
| 2018-10-29 | target/mips: Add emulation of MXU instruction D16MAC | Craig Janeczek |
| 2018-10-29 | target/mips: Add emulation of MXU instruction D16MUL | Craig Janeczek |
| 2018-10-29 | target/mips: Add emulation of MXU instruction S8LDD | Craig Janeczek |
| 2018-10-29 | target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch | Aleksandar Markovic |
| 2018-10-29 | target/mips: Add emulation of MXU instructions S32I2M and S32M2I | Craig Janeczek |
| 2018-10-29 | target/mips: Add emulation of non-MXU MULL within MXU decoding engine | Craig Janeczek |
| 2018-10-29 | target/mips: Add bit encoding for MXU operand getting pattern 'optn3' | Craig Janeczek |
| 2018-10-29 | target/mips: Add bit encoding for MXU operand getting pattern 'optn2' | Craig Janeczek |
| 2018-10-29 | target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2' | Aleksandar Markovic |
| 2018-10-29 | target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2' | Craig Janeczek |
| 2018-10-29 | target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1' | Aleksandar Markovic |
| 2018-10-29 | target/mips: Add MXU decoding engine | Aleksandar Markovic |
| 2018-10-29 | target/mips: Add and integrate MXU decoding engine placeholder | Aleksandar Markovic |
| 2018-10-29 | target/mips: Amend MXU instruction opcodes | Aleksandar Markovic |
| 2018-10-29 | target/mips: Define a bit for MXU in insn_flags | Craig Janeczek |
| 2018-10-29 | target/mips: Introduce MXU registers | Craig Janeczek |
| 2018-10-29 | target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases | Aleksandar Markovic |
| 2018-10-25 | target/mips: Add disassembler support for nanoMIPS | Aleksandar Markovic |
| 2018-10-25 | target/mips: Implement emulation of nanoMIPS EVA instructions | Dimitrije Nikolic |
| 2018-10-25 | target/mips: Add nanoMIPS CRC32 instruction pool | Aleksandar Markovic |
| 2018-10-24 | target/mips: Fix decoding of ALIGN and DALIGN instructions | Aleksandar Markovic |
| 2018-10-24 | target/mips: Fix the title of translate.c | Aleksandar Markovic |
| 2018-10-24 | target/mips: Define the R5900 CPU | Fredrik Noring |
| 2018-10-24 | target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only | Fredrik Noring |
| 2018-10-24 | target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV | Fredrik Noring |
| 2018-10-24 | target/mips: Support R5900 DIV1 and DIVU1 instructions | Fredrik Noring |
| 2018-10-24 | target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions | Fredrik Noring |
| 2018-10-24 | target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions | Fredrik Noring |
| 2018-10-24 | target/mips: Support R5900 three-operand MULT and MULTU instructions | Fredrik Noring |
| 2018-10-24 | target/mips: Add a placeholder for R5900 MMI3 instruction subclass | Fredrik Noring |
| 2018-10-24 | target/mips: Add a placeholder for R5900 MMI2 instruction subclass | Fredrik Noring |
| 2018-10-24 | target/mips: Add a placeholder for R5900 MMI1 instruction subclass | Fredrik Noring |
| 2018-10-24 | target/mips: Add a placeholder for R5900 MMI0 instruction subclass | Fredrik Noring |
| 2018-10-24 | target/mips: Add a placeholder for R5900 MMI instruction class | Fredrik Noring |
| 2018-10-24 | target/mips: Add a placeholder for R5900 LQ | Fredrik Noring |
| 2018-10-24 | target/mips: Add a placeholder for R5900 SQ, handle user mode RDHWR | Fredrik Noring |
