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2018-08-24target/mips: Add definition of nanoMIPS I7200 CPUStefan Markovic
Add definition of the first nanoMIPS processor in QEMU. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Fix ERET/ERETNC behavior related to ADEL exceptionYongbok Kim
Fix ERET/ERETNC so that ADEL exception can be raised. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add updating BadInstr and BadInstrX for nanoMIPSStefan Markovic
Update BadInstr and BadInstrX registers for nanoMIPS. The same support for pre-nanoMIPS remains unimplemented. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add availability control via bit NMSDimitrije Nikolic
A set of nanoMIPS instructions is not available if Config5 bit NMS is set. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of DSP ASE for nanoMIPS - part 6Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 6. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of DSP ASE for nanoMIPS - part 5Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 5. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of DSP ASE for nanoMIPS - part 4Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 4. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of DSP ASE for nanoMIPS - part 3Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 3. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of DSP ASE for nanoMIPS - part 2Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 2. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of DSP ASE for nanoMIPS - part 1Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 1. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Implement MT ASE support for nanoMIPSStefan Markovic
Add emulation of MT ASE instructions for nanoMIPS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Fix pre-nanoMIPS MT ASE instructions availability controlAleksandar Rikalo
Use bits from configuration registers for availability control of MT ASE instructions, rather than only ISA_MT bit in insn_flags. This is done by adding a field in hflags for MT bit, and adding functions check_mt() and check_cp0_mt(). Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS 32-bit branch instructionsStefan Markovic
Add emulation of various flavors of nanoMIPS 32-bit branch instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Implement emulation of nanoMIPS LLWP/SCWP pairAleksandar Rikalo
Implement support for nanoMIPS LLWP/SCWP instructions. Beside adding core functionality of these instructions, this patch adds support for availability control via configuration bit XNP. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add CP0 Config3 and Config5 fields to DisasContext structureDimitrije Nikolic
Add CP0_Config3 and CP0_Config5 to DisasContext structure. This is needed for implementing availability control of various instructions. Reviewed-by: "Aleksandar Markovic <amarkovic@wavecomp.com>" Signed-off-by: "Aleksandar Markovic <amarkovic@wavecomp.com>"
2018-08-24target/mips: Add emulation of nanoMIPS 32-bit load and store instructionsYongbok Kim
Add emulation of various nanoMIPS load and store instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Implement emulation of nanoMIPS EXTW instructionJames Hogan
Implement emulation of nanoMIPS EXTW instruction. EXTW instruction is similar to the MIPS r6 ALIGN instruction, except that it counts the other way and in bits instead of bytes. We therefore generalise gen_align() function into a new gen_align_bits() function (which counts in bits instead of bytes and optimises when bits = size of the word), and implement gen_align() and a new gen_ext() based on that. Since we need to know the word size to check for when the number of bits == the word size, the opc argument is replaced with a wordsz argument (either 32 or 64). Signed-off-by: James Hogan <james.hogan@mips.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-08-24target/mips: Implement emulation of nanoMIPS ROTX instructionMatthew Fortune
Added a helper for ROTX based on the pseudocode from the architecture spec. This instraction was not present in previous MIPS instruction sets. Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-08-24target/mips: Add emulation of misc nanoMIPS instructions (p_lsx)Yongbok Kim
Add emulation of nanoMIPS instructions situated in pool p_lsx, and emulation of LSA instruction as well. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of misc nanoMIPS instructions (pool32axf)Yongbok Kim
Add emulation of misc nanoMIPS instructions situated in pool32axf. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of misc nanoMIPS instructions (pool32a0)Yongbok Kim
Add emulation of nanoMIPS instructions that are situated in pool32a0. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS FP instructionsYongbok Kim
Add emulation of basic floating point arithmetic for nanoMIPS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS 48-bit instructionsYongbok Kim
Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and SWPC48 instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREVYongbok Kim
Add emulation of nanoMIPS instructions MOVE.P and MOVE.PREV. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of some common nanoMIPS 32-bit instructionsYongbok Kim
Add emulation of SIGRIE, SYSCALL, BREAK, SDBBP, ADDIU, ADDIUPC, ADDIUGP.W, LWGP, SWGP, ORI, XORI, ANDI, and other instructions. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS 16-bit save and restore instructionsStefan Markovic
Add emulation of SAVE16 and RESTORE.JRC16 instructions. Routines gen_save(), gen_restore(), and gen_adjust_sp() are provided to support this feature. This patch at the same time provides function gen_op_addr_addi(). This function will be used in emulation of some other nanoMIPS instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS 16-bit logic instructionsYongbok Kim
Add emulation of NOT16, AND16, XOR16, OR16 instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS 16-bit load and store instructionsYongbok Kim
Add emulation of LWXS16, LB16, SB16, LBU16, LH16, SH16, LHU16, LW16, LWSP16, LW4X4, SW4X4, LWGP16, SWSP16, SW16, and SWGP16 instructions. Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS 16-bit misc instructionsYongbok Kim
Add emulation of misc nanoMIPS 16-bit instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS 16-bit shift instructionsYongbok Kim
Add emulation of nanoMIPS 16-bit shift instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS 16-bit branch instructionsStefan Markovic
Add emulation of nanoMIPS 16-bit branch instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructionsYongbok Kim
Add emulation of nanoMIPS 16-bit arithmetic instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add nanoMIPS decoding and extraction utilitiesAleksandar Markovic
Add some basic utility functions and macros for nanoMIPS decoding engine. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add placeholder and invocation of decode_nanomips_opc()Aleksandar Markovic
Add empty body and invocation of decode_nanomips_opc() if the bit ISA_NANOMIPS32 is set in ctx->insn_flags. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Prevent switching mode related to Config3 ISA bit for nanoMIPSStefan Markovic
Only if Config3.ISA is 3 (microMIPS), the mode should be switched in cpu_state_reset(). Config3.ISA is 1 for nanoMIPS processors, and no mode change should happen. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-24target/mips: Add nanoMIPS DSP ASE opcodesStefan Markovic
Add nanoMIPS opcodes for DSP ASE instruction pools and instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add nanoMIPS base instruction set opcodesYongbok Kim
Add nanoMIPS opcodes. nanoMIPS instruction are organized by so-called instruction pools. Each pool contains a set of opcodes, that in turn can be instruction opcodes or instruction pool opcodes. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Add preprocessor constants for nanoMIPSAleksandar Markovic
Add ISA_NANOMIPS32 and CPU_NANOMIPS32 preprocessor constants. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0Yongbok Kim
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only, and placing ELPA flag checks before switch statement were technically correct. However, after adding handling more registers, these checks should be moved to act only in cases of handling EntryLo0 and EntryLo1. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Don't update BadVAddr register in Debug ModeYongbok Kim
BadVAddr should not be updated if (env->hflags & MIPS_HFLAG_DM) is set. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Implement CP0 Config1.WR bit functionalityStefan Markovic
Add testing Config1.WR bit into watch exception handling logic. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Add CP0 BadInstrX registerStefan Markovic
Add CP0 BadInstrX register. This register will be used in nanoMIPS. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Update some CP0 registers bit definitionsAleksandar Markovic
Update CP0 registers Config0, Config1, Config2, Config3, Config4, and Config5 bit definitions. Some of these bits will be utilized by upcoming nanoMIPS changes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Fix two instances of shadow variablesAleksandar Markovic
Fix two instances of shadow variables. This cleans up entire file translate.c from shadow variables. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Mark switch fallthroughs with interpretable commentsAleksandar Markovic
Mark switch fallthroughs with comments, in cases fallthroughs are intentional. The comments "/* fall through */" are interpreted by compilers and other tools, and they will not issue warnings in such cases. For gcc, the warning is turnend on by -Wimplicit-fallthrough. With this patch, there will be no such warnings in target/mips directory. If such warning appears in future, it should be checked if it is intentional, and, if yes, marked with a comment similar to those from this patch. The comment must be just before next "case", otherwise gcc won't understand it. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/mips: Avoid case statements formulated by ranges - part 2Aleksandar Rikalo
Remove "range style" case statements to make code analysis easier. This patch handles cases when the values in the range in question were not properly defined. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <amarkovic@wavecomp.com>
2018-08-16target/mips: Avoid case statements formulated by ranges - part 1Aleksandar Markovic
Remove "range style" case statements to make code analysis easier. This is needed also for some upcoming nanoMIPS-related refactorings. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-06-27target/mips: Fix gdbstub to read/write 64 bit FP registersYongbok Kim
Fix gdbstub to read/write 64 bit FP registers Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Reviewed-by: Aleksandar Markovic <aleksandar.markovic@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
2018-06-27target/mips: Fix data type for offsetYongbok Kim
Offset can be larger than 16 bit from nanoMIPS, and immediate field can be larger than 16 bits as well. Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <aleksandar.markovic@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
2018-06-27target/mips: Update gen_flt_ldst()Yongbok Kim
Update gen_flt_ldst() in order to reuse the functions for nanoMIPS Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <aleksandar.markovic@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
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