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2021-01-14target/mips: Rename translate_init.c as cpu-defs.cPhilippe Mathieu-Daudé
This file is not TCG specific, contains CPU definitions and is consumed by cpu.c. Rename it as such. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201214183739.500368-10-f4bug@amsat.org>
2021-01-14target/mips: Move mmu_init() functions to tlb_helper.cPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-15-f4bug@amsat.org>
2021-01-14target/mips: Fix code style for checkpatch.plPhilippe Mathieu-Daudé
We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201206233949.3783184-14-f4bug@amsat.org>
2021-01-14target/mips: Extract FPU helpers to 'fpu_helper.h'Philippe Mathieu-Daudé
Extract FPU specific helpers from "internal.h" to "fpu_helper.h". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201120210844.2625602-2-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1Philippe Mathieu-Daudé
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing the "Release 1" ISA. Rename it with the 'R1' suffix, as the other CPU definitions do. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-4-f4bug@amsat.org>
2021-01-14target/mips: Replace CP0_Config0 magic values by proper definitionsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201201132817.2863301-3-f4bug@amsat.org>
2020-12-13target/mips: Do not initialize MT registers if MT ASE absentPhilippe Mathieu-Daudé
Do not initialize MT-related config registers if the MT ASE is not present. As some functions access the 'mvp' structure, we still zero-allocate it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201204222622.2743175-4-f4bug@amsat.org>
2020-12-13target/mips: Remove mips_def_t unused argument from mvp_init()Philippe Mathieu-Daudé
mvp_init() doesn't require any CPU definition (beside the information accessible via CPUMIPSState). Remove the unused argument. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201204222622.2743175-2-f4bug@amsat.org>
2020-12-13target/mips: Allow executing MSA instructions on Loongson-3A4000Philippe Mathieu-Daudé
The Loongson-3A4000 is a GS464V-based processor with MIPS MSA ASE: https://www.mail-archive.com/qemu-devel@nongnu.org/msg763059.html Commit af868995e1b correctly set the 'MSA present' bit of Config3 register, but forgot to allow the MSA instructions decoding in insn_flags, so executing them triggers a 'Reserved Instruction'. Fix by adding the ASE_MSA mask to insn_flags. Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Huacai Chen <chenhc@lemote.com> Message-Id: <20201130102228.2395100-1-f4bug@amsat.org>
2020-11-03target/mips: Fix Lesser GPL version numberChetan Pant
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20201016143509.26692-1-chetan4windows@gmail.com> [PMD: Split hw/ vs target/] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-10-17target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)Philippe Mathieu-Daudé
Per "MIPS32 34K Processor Core Family Software User's Manual, Revision 01.13" page 8 in "Joint TLB (JTLB)" section: "The JTLB is a fully associative TLB cache containing 16, 32, or 64-dual-entries mapping up to 128 virtual pages to their corresponding physical addresses." There is no particular reason to restrict the 34Kf core model to 16 TLB entries, so raise its config to 64. This is helpful for other projects, in particular the Yocto Project: Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit MIPS CI loop. It was observed that in this case CI test execution time was almost twice longer than 64bit MIPS variant that runs under MIPS64R2-generic model. It was investigated and concluded that the difference in number of TLBs 16 in 34Kf case vs 64 in MIPS64R2-generic is responsible for most of CI real time execution difference. Because with 16 TLBs linux user-land trashes TLB more and it needs to execute more instructions in TLB refill handler calls, as result it runs much longer. (https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html) Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992 Reported-by: Victor Kamensky <kamensky@cisco.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201016133317.553068-1-f4bug@amsat.org>
2020-10-17target/mips: Fix some comment spelling errorszhaolichang
There are many spelling errors in the comments in target/mips/. Use spellcheck to check the spelling errors. Signed-off-by: zhaolichang <zhaolichang@huawei.com> Reviewed-by: David Edmondson <david.edmondson@oracle.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201009064449.2336-7-zhaolichang@huawei.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini
With Makefiles that have automatically generated dependencies, you generated includes are set as dependencies of the Makefile, so that they are built before everything else and they are available when first building the .c files. Alternatively you can use a fine-grained dependency, e.g. target/arm/translate.o: target/arm/decode-neon-shared.inc.c With Meson you have only one choice and it is a third option, namely "build at the beginning of the corresponding target"; the way you express it is to list the includes in the sources of that target. The problem is that Meson decides if something is a source vs. a generated include by looking at the extension: '.c', '.cc', '.m', '.C' are sources, while everything else is considered an include---including '.inc.c'. Use '.c.inc' to avoid this, as it is consistent with our other convention of using '.rst.inc' for included reStructuredText files. The editorconfig file is adjusted. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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