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2021-04-13target/mips: Fix TCG temporary leak in gen_cache_operation()Philippe Mathieu-Daudé
Fix a TCG temporary leak when translating CACHE opcode. Fixes: 0d74a222c27 ("make ITC Configuration Tags accessible to the CPU") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210406202857.1440744-1-f4bug@amsat.org>
2021-03-13target/mips/tx79: Salvage instructions description commentPhilippe Mathieu-Daudé
This comment describing the tx79 opcodes is helpful. As we will implement these instructions in tx79_translate.c, move the comment there. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-15-f4bug@amsat.org>
2021-03-13target/mips: Remove 'C790 Multimedia Instructions' dead codePhilippe Mathieu-Daudé
We have almost 400 lines of code full of /* TODO */ comments which end calling gen_reserved_instruction(). As we are not going to implement them, and all the caller's switch() default cases already call gen_reserved_instruction(), we can remove this altogether. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-14-f4bug@amsat.org>
2021-03-13target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetreePhilippe Mathieu-Daudé
Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD (Parallel Copy Upper Doubleword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-13-f4bug@amsat.org>
2021-03-13target/mips/tx79: Move PCPYH opcode to decodetreePhilippe Mathieu-Daudé
Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-12-f4bug@amsat.org>
2021-03-13target/mips/translate: Simplify PCPYH using deposit_i64()Philippe Mathieu-Daudé
Simplify the PCPYH (Parallel Copy Halfword) instruction by using multiple calls to deposit_i64() which can be optimized by some TCG backends. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-11-f4bug@amsat.org>
2021-03-13target/mips/translate: Make gen_rdhwr() publicPhilippe Mathieu-Daudé
We will use gen_rdhwr() outside of translate.c, make it public. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-28-f4bug@amsat.org>
2021-03-13target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetreePhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-10-f4bug@amsat.org>
2021-03-13target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetreePhilippe Mathieu-Daudé
Introduce decodetree structure to decode the tx79 opcodes. Start it by moving the existing MFHI1 and MFLO1 opcodes. Remove unnecessary comments. As the TX79 share opcodes with the TX19/TX39/TX49 CPUs, we introduce the decode_ext_txx9() dispatcher where we will add the other decoders later. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-9-f4bug@amsat.org>
2021-03-13target/mips: Use gen_load_gpr[_hi]() when possiblePhilippe Mathieu-Daudé
Use gen_load_gpr[_hi]() instead of open coding it. Patch generated using the following spatch script: @gen_load_gpr@ identifier reg_idx; expression tcg_reg; @@ -if (reg_idx == 0) { - tcg_gen_movi_tl(tcg_reg, 0); -} else { - tcg_gen_mov_tl(tcg_reg, cpu_gpr[reg_idx]); -} +gen_load_gpr(tcg_reg, reg_idx); @gen_load_gpr_hi@ identifier reg_idx; expression tcg_reg; @@ -if (reg_idx == 0) { - tcg_gen_movi_i64(tcg_reg, 0); -} else { - tcg_gen_mov_i64(tcg_reg, cpu_gpr_hi[reg_idx]); -} +gen_load_gpr_hi(tcg_reg, reg_idx); Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210308131604.460693-1-f4bug@amsat.org>
2021-03-13target/mips: Extract MXU code to new mxu_translate.c filePhilippe Mathieu-Daudé
Extract 1600+ lines from the big translate.c into a new file. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-14-f4bug@amsat.org>
2021-03-13target/mips: Introduce mxu_translate_init() helperPhilippe Mathieu-Daudé
Extract the MXU register initialization code from mips_tcg_init() as a new mxu_translate_init() helper. Make it public and replace !TARGET_MIPS64 ifdef'ry by the 'TARGET_LONG_BITS == 32' check to elide this code at preprocessing time. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-13-f4bug@amsat.org>
2021-03-13target/mips: Simplify decode_opc_mxu() ifdef'ryPhilippe Mathieu-Daudé
By making the prototype public and checking 'TARGET_LONG_BITS == 32' we let the compiler elide the decode_opc_mxu() call. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-12-f4bug@amsat.org>
2021-03-13target/mips: Convert decode_ase_mxu() to decodetree prototypePhilippe Mathieu-Daudé
To easily convert MXU code to decodetree, making it return a boolean. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-11-f4bug@amsat.org>
2021-03-13target/mips: Rename decode_opc_mxu() as decode_ase_mxu()Philippe Mathieu-Daudé
Use "decode_{isa,ase,ext}_$name()" function name pattern for public decodetree entrypoints. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-10-f4bug@amsat.org>
2021-03-13target/mips: Move MUL opcode check from decode_mxu() to decode_legacy()Philippe Mathieu-Daudé
Move the check for MUL opcode from decode_opc_mxu() callee to decode_opc_legacy() caller, so we can simplify the ifdef'ry and elide the call in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-9-f4bug@amsat.org>
2021-03-13target/mips: Use OPC_MUL instead of OPC__MXU_MULPhilippe Mathieu-Daudé
We already have a macro and definition to extract / check the Special2 MUL opcode. Use it instead of the unnecessary OPC__MXU_MUL macro. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-8-f4bug@amsat.org>
2021-03-13target/mips: Pass instruction opcode to decode_opc_mxu()Philippe Mathieu-Daudé
In the next commit we'll make decode_opc_mxu() match decodetree prototype by returning a boolean. First pass ctx->opcode as an argument. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-7-f4bug@amsat.org>
2021-03-13target/mips: Remove unused CPUMIPSState* from MXU functionsPhilippe Mathieu-Daudé
None of these MXU functions use their CPUMIPSState* env argument, remove it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-6-f4bug@amsat.org>
2021-03-13target/mips: Remove XBurst Media eXtension Unit dead codePhilippe Mathieu-Daudé
All these unimplemented MXU opcodes end up calling gen_reserved_instruction() which is the default switch case in decode_opc_mxu(). The translate.c file is already big enough and hard to maintain, remove 1300 lines of unnecessary code and /* TODO */ comments. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-5-f4bug@amsat.org>
2021-03-13target/mips: Rewrite complex ifdef'ryPhilippe Mathieu-Daudé
No need for this obfuscated ifdef'ry, KISS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-4-f4bug@amsat.org>
2021-03-10semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé
We want to move the semihosting code out of hw/ in the next patch. This patch contains the mechanical steps, created using: $ git mv include/hw/semihosting/ include/ $ sed -i s,hw/semihosting,semihosting, $(git grep -l hw/semihosting) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210226131356.3964782-2-f4bug@amsat.org> Message-Id: <20210305135451.15427-2-alex.bennee@linaro.org>
2021-02-21target/mips: Use GPR move functions in gen_HILO1_tx79()Philippe Mathieu-Daudé
We have handy functions to access GPR. Use gen_store_gpr() for Move From HI/LO Register and gen_load_gpr() for Move To opcodes. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-8-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpersPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-7-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21target/mips: Rename 128-bit upper halve GPR registersPhilippe Mathieu-Daudé
TCG displays the upper halve registers with the same name as their lower halves. Rename the upper halves with the '[hi]' suffix. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-6-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21target/mips: Promote 128-bit multimedia registers as global onesPhilippe Mathieu-Daudé
The cpu::mmr[] array contains the upper halves of 128-bit GPR registers. While they are only used by the R5900 CPU, the concept is generic and could be used by another MIPS implementation. Rename 'cpu::mmr' as 'cpu::gpr_hi' and make them global. When the code is similar to the GPR lower halves, move it close by. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-5-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21target/mips: Make cpu_HI/LO registers publicPhilippe Mathieu-Daudé
We will access the cpu_HI/LO registers outside of translate.c. Make them publicly accessible. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-4-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-21target/mips: fetch code with translator_ldPhilippe Mathieu-Daudé
Similarly to commits ae82adc8e29..7f93879e444, use the translator_ld*() API introduced in commit 409c1a0bf0f to fetch the code on the MIPS target. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210125105818.2707067-1-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 LL/SC opcodes to decodetreePhilippe Mathieu-Daudé
LL/SC opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-14-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 LLD/SCD opcodes to decodetreePhilippe Mathieu-Daudé
LLD/SCD opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-13-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetreePhilippe Mathieu-Daudé
LDL/LDR/SDL/SDR opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-12-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetreePhilippe Mathieu-Daudé
LWLE/LWRE/SWLE/SWRE (EVA) opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-11-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetreePhilippe Mathieu-Daudé
LWL/LWR/SWL/SWR opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-10-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 CACHE/PREF opcodes to decodetreePhilippe Mathieu-Daudé
CACHE/PREF opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-9-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 COP1X opcode to decodetreePhilippe Mathieu-Daudé
COP1x opcode has been removed from the Release 6. Add a single decodetree entry for it, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() call. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-8-f4bug@amsat.org>
2021-01-14target/mips: Convert Rel6 Special2 opcode to decodetreePhilippe Mathieu-Daudé
Special2 opcode have been removed from the Release 6. Add a single decodetree entry for all the opcode class, triggering Reserved Instruction if ever used. Remove unreachable check_insn_opc_removed() call. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-7-f4bug@amsat.org>
2021-01-14target/mips: Remove now unreachable LSA/DLSA opcodes codePhilippe Mathieu-Daudé
Since we switched to decodetree-generated processing, we can remove this now unreachable code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201208203704.243704-6-f4bug@amsat.org>
2021-01-14target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodesPhilippe Mathieu-Daudé
LSA and LDSA opcodes are also available with MIPS release 6. Introduce the decodetree config files and call the decode() helpers in the main decode_opc() loop. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-24-f4bug@amsat.org>
2021-01-14target/mips: Extract LSA/DLSA translation generatorsPhilippe Mathieu-Daudé
Extract gen_lsa() from translate.c and explode it as gen_LSA() and gen_DLSA(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-22-f4bug@amsat.org>
2021-01-14target/mips: Use decode_ase_msa() generated from decodetreePhilippe Mathieu-Daudé
Now that we can decode the MSA ASE with decode_ase_msa(), use it and remove the previous code, now unreachable. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-21-f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2021-01-14target/mips: Extract MSA translation routinesPhilippe Mathieu-Daudé
Extract 2200 lines from the huge translate.c to a new file, 'msa_translate.c'. As there are too many inter-dependencies we don't compile it as another object yet, but keep including it in the big translate.o. We gain in code maintainability. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201120210844.2625602-5-f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2021-01-14target/mips: Declare gen_msa/_branch() in 'translate.h'Philippe Mathieu-Daudé
Make gen_msa() and gen_msa_branch() public declarations so we can keep calling them once extracted from the big translate.c in the next commit. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-18-f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2021-01-14target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()Philippe Mathieu-Daudé
In preparation of using the decodetree script, explode gen_msa_branch() as following: - OPC_BZ_V -> BxZ_V(EQ) - OPC_BNZ_V -> BxZ_V(NE) - OPC_BZ_[BHWD] -> BxZ(false) - OPC_BNZ_[BHWD] -> BxZ(true) Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-10-f4bug@amsat.org>
2021-01-14target/mips: Remove CPUMIPSState* argument from gen_msa*() methodsPhilippe Mathieu-Daudé
The gen_msa*() methods don't use the "CPUMIPSState *env" argument. Remove it to simplify. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-9-f4bug@amsat.org>
2021-01-14target/mips: Extract msa_translate_init() from mips_tcg_init()Philippe Mathieu-Daudé
The msa_wr_d[] registers are only initialized/used by MSA. They are declared static. We want to move them to the new 'msa_translate.c' unit in few commits, without having to declare them global (with extern). Extract first the logic initialization of the MSA registers from the generic initialization. We will later move this function along with the MSA registers to the new C unit. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-8-f4bug@amsat.org>
2021-01-14target/mips: Alias MSA vector registers on FPU scalar registersPhilippe Mathieu-Daudé
Commits 863f264d10f ("add msa_reset(), global msa register") and cb269f273fd ("fix multiple TCG registers covering same data") removed the FPU scalar registers and replaced them by aliases to the MSA vector registers. It is not very clear to have FPU registers displayed with MSA register names, even if MSA ASE is not present. Instead of aliasing FPU registers to the MSA ones (even when MSA is absent), we now alias the MSA ones to the FPU ones (only when MSA is present). Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-7-f4bug@amsat.org>
2021-01-14target/mips: Simplify MSA TCG logicPhilippe Mathieu-Daudé
Only decode MSA opcodes if MSA is present (implemented). Now than check_msa_access() will only be called if MSA is present, the only way to have MIPS_HFLAG_MSA unset is if MSA is disabled (bit CP0C5_MSAEn cleared, see previous commit). Therefore we can remove the 'reserved instruction' exception. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-5-f4bug@amsat.org>
2021-01-14target/mips: Introduce ase_msa_available() helperPhilippe Mathieu-Daudé
Instead of accessing CP0_Config3 directly and checking the 'MSA Present' bit, introduce an explicit helper, making the code easier to read. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201208003702.4088927-2-f4bug@amsat.org>
2021-01-14target/mips/translate: Expose check_mips_64() to 32-bit modePhilippe Mathieu-Daudé
To allow compiling 64-bit specific translation code more generically (and removing #ifdef'ry), allow compiling check_mips_64() on 32-bit targets. If ever called on 32-bit, we obviously emit a reserved instruction exception. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201215225757.764263-3-f4bug@amsat.org>
2021-01-14target/mips/translate: Extract decode_opc_legacy() from decode_opc()Philippe Mathieu-Daudé
As we will slowly move to decodetree generated decoders, extract the legacy decoding from decode_opc(), so new decoders are added in decode_opc() while old code is removed from decode_opc_legacy(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-2-f4bug@amsat.org>
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