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path: root/target/mips/translate.c
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2017-07-17target/mips: optimize WSBH, DSBH and DSHDAurelien Jarno
Use the same mask to avoid having to load two different constants. Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-11target/mips: fix msa copy_[s|u]_df rd = 0 corner caseMiodrag Dinic
This patch fixes the msa copy_[s|u]_df instruction emulation when the destination register rd is zero. Without this patch the zero register would get clobbered, which should never happen because it is supposed to be hardwired to 0. Fix this corner case by explicitly checking rd = 0 and effectively making these instructions emulation no-op in that case. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-06-05target/mips: optimize indirect branchesAurelien Jarno
Cc: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170430145254.25616-4-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-05target/mips: optimize cross-page direct jumps in softmmuAurelien Jarno
Cc: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20170430145254.25616-3-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-03-20target/mips: fix delay slot detection in gen_msa_branch()Yongbok Kim
It is unnecessary to test R6 from delay/forbidden slot check in gen_msa_branch(). https://bugs.launchpad.net/qemu/+bug/1663287 Reported-by: Brian Campbell <bacam@z273.org.uk> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-03-20target-mips: replace few LOG_DISAS() with trace pointsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-03-20target-mips: replace break by goto cp0_unimplementedPhilippe Mathieu-Daudé
this fixes many warnings like: target/mips/translate.c:6253:13: warning: Value stored to 'rn' is never read rn = "invalid sel"; ^ ~~~~~~~~~~~~~ Reported-by: Clang Static Analyzer Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-03-20target-mips: log bad coprocessor0 register accesses with LOG_UNIMPPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-03-20target-mips: remove old & unuseful commentsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-02-21target-mips: Provide function to test if a CPU supports an ISAPaul Burton
Provide a new cpu_supports_isa function which allows callers to determine whether a CPU supports one of the ISA_ flags, by testing whether the associated struct mips_def_t sets the ISA flags in its insn_flags field. An example use of this is to allow boards which generate bootloader code to determine the properties of the CPU that will be used, for example whether the CPU is 64 bit or which architecture revision it implements. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-01-10target-mips: Use clz opcodeRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-mips: Use the new extract opRichard Henderson
Use extract for EXT and DEXT. Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-12-20Move target-* CPU file into a target/ folderThomas Huth
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
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