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2023-11-19target/mips: Fix TX79 LQ/SQ opcodesPhilippe Mathieu-Daudé
The base register address offset is *signed*. Cc: qemu-stable@nongnu.org Fixes: aaaa82a9f9 ("target/mips/tx79: Introduce LQ opcode (Load Quadword)") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914090447.12557-1-philmd@linaro.org> (cherry picked from commit 18f86aecd6a1bea0f78af14587a684ad966d8d3a) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-11-19target/mips: Fix MSA BZ/BNZ opcodes displacementPhilippe Mathieu-Daudé
The PC offset is *signed*. Cc: qemu-stable@nongnu.org Reported-by: Sergey Evlashev <vectorchiefrocks@gmail.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1624 Fixes: c7a9ef7517 ("target/mips: Introduce decode tree bindings for MSA ASE") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914085807.12241-1-philmd@linaro.org> (cherry picked from commit 04591b3ddd9a96b9298a1dd437a6464ab55e62ee) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2022-11-08target/mips: Don't check COP1X for 64 bit FP modeJiaxun Yang
Some implementations (i.e. Loongson-2F) may decide to implement a 64 bit FPU without implementing COP1X instructions. As the eligibility of 64 bit FP instructions is already determined by CP0St_FR, there is no need to check for COP1X again. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221102165719.190378-1-jiaxun.yang@flygoat.com> [PMD: Add missing trailing parenthesis (buildfix)] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-11-08target/mips: Enable LBX/LWX/* instructions for OcteonPavel Dovgalyuk
This patch changes condition and function name for enabling indexed load instructions for Octeon vCPUs. Octeons do not have DSP extension, but implement LBX-and-others. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <166728058455.229236.13834649461181619195.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-11-08target/mips: Cast offset field of Octeon BBIT to int16_tJiaxun Yang
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference Manual" offset field is signed 16 bit value. However arg_BBIT.offset is unsigned. We need to cast it as signed to do address calculation. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221031132531.18122-3-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-26target/mips: Convert to tcg_ops restore_state_to_opcRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-10-04accel/tcg: Introduce tb_pc and log_pcRichard Henderson
The availability of tb->pc will shortly be conditional. Introduce accessor functions to minimize ifdefs. Pass around a known pc to places like tcg_gen_code, where the caller must already have the value. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-13target/mips: Honour -semihosting-config userspace=onPeter Maydell
Honour the commandline -semihosting-config userspace=on option, instead of always permitting userspace semihosting calls in system emulation mode, by passing the correct value to the is_userspace argument of semihosting_enabled(). Note that this is a behaviour change: if the user wants to do semihosting calls from userspace they must now specifically enable them on the command line. MIPS semihosting is not implemented for linux-user builds. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220822141230.3658237-5-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-06accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson
Pass these along to translator_loop -- pc may be used instead of tb->pc, and host_pc is currently unused. Adjust all targets at one time. Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-08-08target/mips: Handle lock_user() failure in UHI_plog semihosting callPeter Maydell
Coverity notes that we forgot to check the error return from lock_user() in one place in the handling of the UHI_plog semihosting call. Add the missing error handling. report_fault() is rather brutal in that it will call abort(), but this is the same error-handling used in the rest of this file. Resolves: Coverity CID 1490684 Fixes: ea4210600db3c5 ("target/mips: Avoid qemu_semihosting_log_out for UHI_plog") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220719191737.384744-1-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-08-02target/mips: Advance pc after semihosting exceptionRichard Henderson
Delay generating the exception until after we know the insn length, and record that length in env->error_code. Fixes: 8ec7e3c53d4 ("target/mips: Use an exception for semihosting") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1126 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-12target/mips: Remove GET_TARGET_STRING and FREE_TARGET_STRINGRichard Henderson
Inline these macros into the only two callers. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220628111701.677216-9-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: Simplify UHI_argnlen and UHI_argnRichard Henderson
With semihosting_get_arg, we already have a check vs argc, so there's no point replicating it -- just check the result vs NULL. Merge copy_argn_to_target into its caller. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220628111701.677216-8-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: Use error_report for UHI_assertRichard Henderson
Always log the assert locally. Do not report_fault, but instead include the fact of the fault in the assertion. Don't bother freeing allocated strings before the abort(). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220628111701.677216-6-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: Avoid qemu_semihosting_log_out for UHI_plogRichard Henderson
Use semihost_sys_write and/or qemu_semihosting_console_write for implementing plog. When using gdbstub, copy the temp string below the stack so that gdb has a guest address from which to perform the log. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220628111701.677216-5-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: Use semihosting/syscalls.hRichard Henderson
This separates guest file descriptors from host file descriptors, and utilizes shared infrastructure for integration with gdbstub. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220628111701.677216-4-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: Drop link syscall from semihostingRichard Henderson
We don't implement it with _WIN32 hosts, and the syscall is missing from the gdb remote file i/o interface. Since we can't implement it universally, drop it. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220628111701.677216-3-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: Create report_fault for semihostingRichard Henderson
The UHI specification does not have an EFAULT value, and further specifies that "undefined UHI operations should not return control to the target". So, log the error and abort. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220628111701.677216-2-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: implement Octeon-specific arithmetic instructionsPavel Dovgalyuk
This patch implements several Octeon-specific instructions: - BADDU - DMUL - EXTS/EXTS32 - CINS/CINS32 - POP/DPOP - SEQ/SEQI - SNE/SNEI Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <165572673245.167724.17377788816335619000.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: implement Octeon-specific BBIT instructionsPavel Dovgalyuk
This patch introduces Octeon-specific decoder and implements check-bit-and-jump instructions. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <165572672705.167724.16667636081912075906.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-07-12target/mips: introduce decodetree structure for Cavium Octeon extensionPavel Dovgalyuk
This patch adds decodetree for Cavium Octeon extension and an instruction set extension flag for using it in CPU models. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <165572672162.167724.13656301229517693806.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-06-28target/mips: Drop pread and pwrite syscalls from semihostingRichard Henderson
We don't implement it with _WIN32 hosts, and the syscalls are missing from the gdb remote file i/o interface. Since we can't implement them universally, drop them. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28target/mips: Add UHI errno valuesRichard Henderson
From the Unified Hosting Interface, MD01069 Reference Manual, version 1.1.6, 06 July 2015. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28target/mips: Use an exception for semihostingRichard Henderson
Within do_interrupt, we hold the iothread lock, which is required for Chardev access for the console, and for the round trip for use_gdb_syscalls(). Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Move exec/softmmu-semi.h to semihosting/softmmu-uaccess.hRichard Henderson
We have a subdirectory for semihosting; move this file out of exec. Rename to emphasize the contents are a replacement for the functions in linux-user/bsd-user uaccess.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-11target/mips: Add missing default cases for some nanoMIPS poolsStefan Pejic
Switch statements for the code segments that handle nanoMIPS instruction pools P.LL, P.SC, P.SHIFT, P.LS.S1, P.LS.E0, PP.LSXS do not have proper default case, resulting in not generating reserved instruction exception for certain illegal opcodes. Fix this by adding default cases for these switch statements that trigger reserved instruction exception. Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220504110403.613168-7-stefan.pejic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-06-11target/mips: Fix handling of unaligned memory access for nanoMIPS ISADragan Mladjenovic
nanoMIPS ISA does not support unaligned memory access. Adjust DisasContext's default_tcg_memop_mask to reflect this. Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220504110403.613168-6-stefan.pejic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-06-11target/mips: Fix emulation of nanoMIPS BNEC[32] instructionDragan Mladjenovic
If both rs and rt are the same register, the nanoMIPS instruction BNEC[32] rs, rt, address is equivalent to NOP (branch is not taken and there is no delay slot). This commit provides such behavior. Without this commit, this scenario results in an incorrect behavior. Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220504110403.613168-5-stefan.pejic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-06-11target/mips: Fix emulation of nanoMIPS BPOSGE32C instructionDragan Mladjenovic
There are currently two problems related to the emulation of the instruction BPOSGE32C. The nanoMIPS instruction BPOSGE32C belongs to DSP R3 instructions (actually, as of now, it is the only instruction of DSP R3). The presence of DSP R3 instructions in QEMU is indicated by the flag MIPS_HFLAG_DSP_R3 (0x20000000). This flag is currently being properly set in CPUMIPSState's hflags (for example, for I7200 nanoMIPS CPU). However, it is not propagated to DisasContext's hflags, since the flag MIPS_HFLAG_DSP_R3 is not set in MIPS_HFLAG_TMASK (while similar flags MIPS_HFLAG_DSP_R2 and MIPS_HFLAG_DSP are set in this mask, and there is no problem in functioning check_dsp_r2(), check_dsp()). This means the function check_dsp_r3() currently does not work properly, and the emulation of BPOSGE32C can not work properly as well. Change MIPS_HFLAG_TMASK from 0x1F5807FF to 0x3F5807FF (logical OR with 0x20000000) to fix this. Additionally, check_cp1_enabled() is currently incorrectly called while emulating BPOSGE32C. BPOSGE32C is in the same pool (P.BR1) as FPU branch instruction BC1EQZC and BC1NEZC, but it not a part of FPU (CP1) instructions, and check_cp1_enabled() should not be involved while emulating BPOSGE32C. Rearrange invocations of check_cp1_enabled() within P.BR1 pool handling to affect only BC1EQZC and BC1NEZC emulation, and not BPOSGE32C emulation. Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220504110403.613168-4-stefan.pejic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-06-11target/mips: Fix emulation of nanoMIPS EXTRV_S.H instructionDragan Mladjenovic
The field rs in the instruction EXTRV_S.H rt, ac, rs is specified in nanoMIPS documentation as opcode[20..16]. It is, however, erroneously considered as opcode[25..21] in the current QEMU implementation. In function gen_pool32axf_2_nanomips_insn(), the variable v0_t corresponds to rt/opcode[25..21], and v1_t corresponds to rs/opcode[20..16]), and v0_t is by mistake passed to the helper gen_helper_extr_s_h(). Use v1_t rather than v0_t in the invocation of gen_helper_extr_s_h() to fix this. Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com> Fixes: 8b3698b294 ("target/mips: Add emulation of DSP ASE for nanoMIPS") Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220504110403.613168-3-stefan.pejic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-06-11target/mips: Fix emulation of nanoMIPS MTHLIP instructionStefan Pejic
The field ac in nanoMIPS instruction MTHLIP rs, ac is specified in nanoMIPS documentation as opcode[15..14] (2 bits). However, in the current QEMU code, the corresponding argument passed to the helper gen_helper_mthlip() has the value of opcode[15..11] (5 bits). Right shift the value of this argument by three bits to fix this. Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220504110403.613168-2-stefan.pejic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-06-11target/mips: Fix FTRUNC_S and FTRUNC_U trans helperNi Hui
Fix the FTRUNC_S and FTRUNC_U trans helper problem. Fixes: 5c5b64000c ("target/mips: Convert MSA 2RF instruction format to decodetree") Signed-off-by: nihui <shuizhuyuanluo@126.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220503144241.289239-1-shuizhuyuanluo@126.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-06-11target/mips: Fix store adress of high 64bit in helper_msa_st_b()Ni Hui
This patch fix the issue that helper_msa_st_b() write high 64bit data to where the low 64bit resides, leaving high 64bit undefined. Fixes: 68ad9260e0 ("target/mips: Use 8-byte memory ops for msa load/store") Signed-off-by: Ni Hui <shuizhuyuanluo@126.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220504023319.12923-1-shuizhuyuanluo@126.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-06-11target/mips: Do not treat msa INSERT as NOP when wd is zeroNi Hui
Only for msa COPY_U/COPY_S with wd zero, we treat it as NOP. Move this special rule into COPY_U and COPY_S trans function. Fixes: 97fe675519 ("target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree") Signed-off-by: Ni Hui <shuizhuyuanluo@126.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220503130708.272850-4-shuizhuyuanluo@126.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-06-11target/mips: Fix msa checking condition in trans_msa_elm_fn()Ni Hui
Fix issue that condition of check_msa_enabled(ctx) is reversed that causes segfault when msa elm_fn op encountered. Fixes: 2f2745c81a ("target/mips: Convert MSA COPY_U opcode to decodetree") Fixes: 97fe675519 ("target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree") Signed-off-by: Ni Hui <shuizhuyuanluo@126.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220503130708.272850-3-shuizhuyuanluo@126.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-06-11target/mips: Fix df_extract_val() and df_extract_df() dfe lookupNi Hui
Actually look into dfe structure data so that df_extract_val() and df_extract_df() can return immediate and datafield other than BYTE. Fixes: 4701d23aef ("target/mips: Convert MSA BIT instruction format to decodetree") Signed-off-by: Ni Hui <shuizhuyuanluo@126.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220503130708.272850-2-shuizhuyuanluo@126.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-06-11target/mips: Fix SAT_S trans helperNi Hui
Fix the SAT_S and SAT_U trans helper confusion. Fixes: 4701d23aef ("target/mips: Convert MSA BIT instruction format to decodetree") Signed-off-by: Ni Hui <shuizhuyuanluo@126.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220503130708.272850-1-shuizhuyuanluo@126.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-06-11target/mips: Fix WatchHi.M handlingMarcin Nowakowski
bit 31 (M) of WatchHiN register is a read-only register indicating whether the next WatchHi register is present. It must not be reset during user writes to the register. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com> Reviewed-by: David Daney <david.daney@fungible.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@fungible.com> Message-Id: <20220511212953.74738-1-philmd@fungible.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau
G_NORETURN was introduced in glib 2.68, fallback to G_GNUC_NORETURN in glib-compat. Note that this attribute must be placed before the function declaration (bringing a bit of consistency in qemu codebase usage). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-Id: <20220420132624.2439741-20-marcandre.lureau@redhat.com>
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson
We have fetched and locked the logfile in translator_loop. Pass the filepointer down to the disas_log hook so that it need not be fetched and locked again. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220417183019.755276-13-richard.henderson@linaro.org>
2022-04-06Replace TARGET_WORDS_BIGENDIANMarc-André Lureau
Convert the TARGET_WORDS_BIGENDIAN macro, similarly to what was done with HOST_BIG_ENDIAN. The new TARGET_BIG_ENDIAN macro is either 0 or 1, and thus should always be defined to prevent misuse. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Suggested-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-8-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau
Replace a config-time define with a compile time condition define (compatible with clang and gcc) that must be declared prior to its usage. This avoids having a global configure time define, but also prevents from bad usage, if the config header wasn't included before. This can help to make some code independent from qemu too. gcc supports __BYTE_ORDER__ from about 4.6 and clang from 3.2. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> [ For the s390x parts I'm involved in ] Acked-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-7-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-21exec/exec-all: Move 'qemu/log.h' include in units requiring itPhilippe Mathieu-Daudé
Many files use "qemu/log.h" declarations but neglect to include it (they inherit it via "exec/exec-all.h"). "exec/exec-all.h" is a core component and shouldn't be used that way. Move the "qemu/log.h" inclusion locally to each unit requiring it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220207082756.82600-10-f4bug@amsat.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-01-11target/mips: Extract trap code into env->error_codeRichard Henderson
Simplify cpu_loop by doing all of the decode in translate. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-18-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-11target/mips: Extract break code into env->error_codeRichard Henderson
Simplify cpu_loop by doing all of the decode in translate. This fixes a bug in that cpu_loop was not handling the different layout of the R6 version of break16. This fixes a bug in that cpu_loop extracted the wrong bits for the mips16e break16 instruction. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-17-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot
Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-11-02Merge remote-tracking branch 'remotes/philmd/tags/mips-20211102' into stagingRichard Henderson
MIPS patches queue - Fine-grained MAINTAINERS sections - Fix MSA MADDV.B / MSUBV.B opcodes - Convert MSA opcodes to decodetree - Correct Loongson-3A4000 MSAIR register - Do not accept ELF nanoMIPS binaries on linux-user - Use ISA instead of PCI interrupts in VT82C686 PCI device # gpg: Signature made Tue 02 Nov 2021 09:41:04 AM EDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * remotes/philmd/tags/mips-20211102: (41 commits) Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too" hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts usb/uhci: Replace pci_set_irq with qemu_set_irq usb/uhci: Disallow user creating a vt82c686-uhci-pci device usb/uhci: Misc clean up target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU target/mips: Fix Loongson-3A4000 MSAIR config register target/mips: Remove one MSA unnecessary decodetree overlap group target/mips: Remove generic MSA opcode target/mips: Convert CTCMSA opcode to decodetree target/mips: Convert CFCMSA opcode to decodetree target/mips: Convert MSA MOVE.V opcode to decodetree target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree target/mips: Convert MSA COPY_U opcode to decodetree target/mips: Convert MSA ELM instruction format to decodetree target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02target/mips: Remove one MSA unnecessary decodetree overlap groupPhilippe Mathieu-Daudé
Only the MSA generic opcode was overlapping with the other instructions. Since the previous commit removed it, we can now remove the overlap group. The decodetree script forces us to re-indent the opcodes. Diff trivial to review using `git-diff --ignore-all-space`. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-32-f4bug@amsat.org>
2021-11-02target/mips: Remove generic MSA opcodePhilippe Mathieu-Daudé
All opcodes have been converted to decodetree. The generic MSA handler is now pointless, remove it. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-31-f4bug@amsat.org>
2021-11-02target/mips: Convert CTCMSA opcode to decodetreePhilippe Mathieu-Daudé
Convert the CTCMSA (Copy To Control MSA register) opcode to decodetree. Since it overlaps with the SLDI opcode, use a decodetree overlap group. Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-30-f4bug@amsat.org>
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