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2021-06-24target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful casesPhilippe Mathieu-Daudé
These switch cases for the microMIPS BPOSGE32 / BPOSGE64 opcodes have been added commit 3c824109da0 ("target-mips: microMIPS ASE support"). More than 11 years later it is safe to assume there won't be added soon. The cases fall back to the default which generates a RESERVED INSTRUCTION, so it is safe to remove them. Functionally speaking, the patch is a no-op. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-8-f4bug@amsat.org>
2021-06-24target/mips: Remove SmartMIPS / MDMX unuseful commentsPhilippe Mathieu-Daudé
These placeholder comments for SmartMIPS and MDMX extensions have been added commit 3c824109da0 ("target-mips: microMIPS ASE support"). More than 11 years later it is safe to assume there won't be added soon, so remove these unuseful comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-7-f4bug@amsat.org>
2021-06-24target/mips: Move translate.h to tcg/ sub directoryPhilippe Mathieu-Daudé
We moved various TCG source files in commit a2b0a27d33e ("target/mips: Move TCG source files under tcg/ sub directory") but forgot to move the header declaring their prototypes. Do it now, since all it declares is TCG specific. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-5-f4bug@amsat.org>
2021-06-24target/mips: Move TCG trace events to tcg/ sub directoryPhilippe Mathieu-Daudé
Commit a2b0a27d33e ("target/mips: Move TCG source files under tcg/ sub directory") forgot to move the trace-event file. As it only contains TCG events, move it for consistency. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-4-f4bug@amsat.org>
2021-06-24target/mips: Do not abort on invalid instructionPhilippe Mathieu-Daudé
On real hardware an invalid instruction doesn't halt the world, but usually triggers a RESERVED INSTRUCTION exception. TCG guest code shouldn't abort QEMU anyway. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-2-f4bug@amsat.org>
2021-06-24target/mips: Raise exception when DINSV opcode used with DSP disabledPhilippe Mathieu-Daudé
Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02, Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module": If the Module/ASE is not implemented, executing such an instruction must cause a Reserved Instruction Exception. The DINSV instruction lists the following exceptions: - Reserved Instruction - DSP Disabled If the MIPS core doesn't support the DSP module, or the DSP is disabled, do not handle the '$rt = $0' case as a no-op but raise the proper exception instead. Cc: Jia Liu <proljc@gmail.com> Fixes: 1cb6686cf92 ("target-mips: Add ASE DSP bit/manipulation instructions") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210529165443.1114402-1-f4bug@amsat.org>
2021-06-24target/mips: Fix more TCG temporary leaks in gen_pool32a5_nanomips_insnPhilippe Mathieu-Daudé
Fix multiple TCG temporary leaks in gen_pool32a5_nanomips_insn(). Fixes: 3285a3e4445 ("target/mips: Add emulation of DSP ASE for nanoMIPS - part 1") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210617174323.2900831-3-f4bug@amsat.org>
2021-06-24target/mips: Fix TCG temporary leaks in gen_pool32a5_nanomips_insn()Philippe Mathieu-Daudé
Fix a pair of TCG temporary leak when translating nanoMIPS SHILO opcode. Fixes: 3285a3e4445 ("target/mips: Add emulation of DSP ASE for nanoMIPS") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210530094538.1275329-1-f4bug@amsat.org>
2021-06-24target/mips: Fix potential integer overflow (CID 1452921)Philippe Mathieu-Daudé
Use the BIT_ULL() macro to ensure we use 64-bit arithmetic. This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN): CID 1452921: Integer handling issues: Potentially overflowing expression "1 << w" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). Fixes: 074cfcb4dae ("target/mips: Implement hardware page table walker") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210505215119.1517465-1-f4bug@amsat.org>
2021-06-05target/mips: Fix 'Uncoditional' typoPhilippe Mathieu-Daudé
Fix Uncoditional -> Unconditional typo. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Message-Id: <20210602170759.2500248-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-26target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failedRichard Henderson
Add a flag to MIPSCPUClass in order to avoid needing to replace mips_tcg_ops.do_transaction_failed. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20210227232519.222663-2-richard.henderson@linaro.org>
2021-05-02target/mips: Move TCG source files under tcg/ sub directoryPhilippe Mathieu-Daudé
To ease maintenance, move all TCG specific files under the tcg/ sub-directory. Adapt the Meson machinery. The following prototypes: - mips_tcg_init() - mips_cpu_do_unaligned_access() - mips_cpu_do_transaction_failed() can now be restricted to the "tcg-internal.h" header. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-29-f4bug@amsat.org>
2021-05-02target/mips: Move exception management code to exception.cPhilippe Mathieu-Daudé
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-27-f4bug@amsat.org>
2021-05-02target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.cPhilippe Mathieu-Daudé
Move TLB management helpers to tcg/sysemu/tlb_helper.c. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-26-f4bug@amsat.org>
2021-05-02target/mips: Move helper_cache() to tcg/sysemu/special_helper.cPhilippe Mathieu-Daudé
Move helper_cache() to tcg/sysemu/special_helper.c. The CACHE opcode is privileged and is not accessible in user emulation. However we get a link failure when restricting the symbol to sysemu. For now, add a stub helper to satisfy linking, which abort if ever called. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-25-f4bug@amsat.org>
2021-05-02target/mips: Move Special opcodes to tcg/sysemu/special_helper.cPhilippe Mathieu-Daudé
Move the Special opcodes helpers to tcg/sysemu/special_helper.c. Since mips_io_recompile_replay_branch() is set as CPUClass::io_recompile_replay_branch handler in cpu.c, we need to declare its prototype in "tcg-internal.h". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-24-f4bug@amsat.org>
2021-05-02target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scopePhilippe Mathieu-Daudé
The 3 map_address() handlers are local to tlb_helper.c, no need to have their prototype declared publically. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-23-f4bug@amsat.org>
2021-05-02target/mips: Move tlb_helper.c to tcg/sysemu/Philippe Mathieu-Daudé
Move tlb_helper.c to the tcg/sysemu/ subdir, along with the following 3 declarations to tcg-internal.h: - cpu_mips_tlb_flush() - cpu_mips_translate_address() - r4k_invalidate_tlb() Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/ are only build when sysemu mode is configured. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-22-f4bug@amsat.org>
2021-05-02target/mips: Restrict mmu_init() to TCGPhilippe Mathieu-Daudé
mmu_init() is only required by TCG accelerator. Restrict its declaration and call to TCG. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-21-f4bug@amsat.org>
2021-05-02target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolderPhilippe Mathieu-Daudé
Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder, adapting the Meson machinery. Move the opcode definitions to tcg/sysemu_helper.h.inc. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-20-f4bug@amsat.org>
2021-05-02target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCGPhilippe Mathieu-Daudé
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-19-f4bug@amsat.org>
2021-05-02target/mips: Add simple user-mode mips_cpu_tlb_fill()Philippe Mathieu-Daudé
tlb_helper.c's #ifdef'ry hides a quite simple user-mode implementation of mips_cpu_tlb_fill(). Copy the user-mode implementation (without #ifdef'ry) to tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry. This will allow us to restrict tlb_helper.c to sysemu. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-15-f4bug@amsat.org>
2021-05-02target/mips: Add simple user-mode mips_cpu_do_interrupt()Philippe Mathieu-Daudé
The #ifdef'ry hides that the user-mode implementation of mips_cpu_do_interrupt() simply sets exception_index = EXCP_NONE. Add this simple implementation to tcg/user/tlb_helper.c, and the corresponding Meson machinery to build this file when user emulation is configured. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-14-f4bug@amsat.org>
2021-05-02target/mips: Introduce tcg-internal.h for TCG specific declarationsPhilippe Mathieu-Daudé
We will gradually move TCG-specific declarations to a new local header: "tcg-internal.h". To keep review simple, first add this header with 2 TCG prototypes, which we are going to move in the next 2 commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-13-f4bug@amsat.org>
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