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2022-06-11target/mips: Fix store adress of high 64bit in helper_msa_st_b()Ni Hui
This patch fix the issue that helper_msa_st_b() write high 64bit data to where the low 64bit resides, leaving high 64bit undefined. Fixes: 68ad9260e0 ("target/mips: Use 8-byte memory ops for msa load/store") Signed-off-by: Ni Hui <shuizhuyuanluo@126.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220504023319.12923-1-shuizhuyuanluo@126.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-04-06Replace TARGET_WORDS_BIGENDIANMarc-André Lureau
Convert the TARGET_WORDS_BIGENDIAN macro, similarly to what was done with HOST_BIG_ENDIAN. The new TARGET_BIG_ENDIAN macro is either 0 or 1, and thus should always be defined to prevent misuse. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Suggested-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-8-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau
Replace a config-time define with a compile time condition define (compatible with clang and gcc) that must be declared prior to its usage. This avoids having a global configure time define, but also prevents from bad usage, if the config header wasn't included before. This can help to make some code independent from qemu too. gcc supports __BYTE_ORDER__ from about 4.6 and clang from 3.2. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> [ For the s390x parts I'm involved in ] Acked-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-7-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-11-02target/mips: Fix MSA MSUBV.B opcodePhilippe Mathieu-Daudé
The result of the 'Vector Multiply and Subtract' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 5f148a02327 mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix that. Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Fixes: 5f148a02327 ("target/mips: msa: Split helpers for MSUBV.<B|H|W|D>") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-3-f4bug@amsat.org>
2021-11-02target/mips: Fix MSA MADDV.B opcodePhilippe Mathieu-Daudé
The result of the 'Vector Multiply and Add' opcode is incorrect with Byte vectors. Probably due to a copy/paste error, commit 7a7a162adde mistakenly used the $wt (target register) instead of $wd (destination register) as first operand. Fix that. Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Fixes: 7a7a162adde ("target/mips: msa: Split helpers for MADDV.<B|H|W|D>") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211028210843.2120802-2-f4bug@amsat.org>
2021-10-13target/mips: Use 8-byte memory ops for msa load/storeRichard Henderson
Rather than use 4-16 separate operations, use 2 operations plus some byte reordering as necessary. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-13target/mips: Use cpu_*_data_ra for msa load/storeRichard Henderson
We should not have been using the helper_ret_* set of functions, as they are supposed to be private to tcg. Nor should we have been using the plain cpu_*_data set of functions, as they do not handle unwinding properly. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-05tcg: Rename TCGMemOpIdx to MemOpIdxRichard Henderson
We're about to move this out of tcg.h, so rename it as we did when moving MemOp. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-02target/mips: Move TCG source files under tcg/ sub directoryPhilippe Mathieu-Daudé
To ease maintenance, move all TCG specific files under the tcg/ sub-directory. Adapt the Meson machinery. The following prototypes: - mips_tcg_init() - mips_cpu_do_unaligned_access() - mips_cpu_do_transaction_failed() can now be restricted to the "tcg-internal.h" header. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-29-f4bug@amsat.org>