| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-09-21 | mips: introduce internal.h and cleanup cpu.h | Philippe Mathieu-Daudé |
| 2017-08-02 | target-mips: apply CP0.PageMask before writing into TLB entry | Leon Alrae |
| 2017-07-20 | target/mips: Add segmentation control registers | James Hogan |
| 2017-07-20 | target/mips: Add an MMU mode for ERL | James Hogan |
| 2017-07-20 | target/mips: Abstract mmu_idx from hflags | James Hogan |
| 2017-07-20 | target/mips: Add CP0_Ebase.WG (write gate) support | James Hogan |
| 2017-07-20 | target/mips: Weaken TLB flush on UX,SX,KX,ASID changes | James Hogan |
| 2017-07-20 | target/mips: Fix TLBWI shadow flush for EHINV,XI,RI | James Hogan |
| 2017-03-09 | target/mips: hold BQL for timer interrupts | Yongbok Kim |
| 2017-01-13 | cputlb: drop flush_global flag from tlb_flush | Alex Bennée |
| 2017-01-10 | target-mips: Use clz opcode | Richard Henderson |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth |
 |
index : slackcoder/qemu | |
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