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path: root/target/mips/helper.c
AgeCommit message (Expand)Author
2020-12-13target/mips: Move mips_cpu_add_definition() from helper.c to cpu.cPhilippe Mathieu-Daudé
2020-12-13target/mips: Introduce ase_mt_available() helperPhilippe Mathieu-Daudé
2020-12-13target/mips: Also display exception names in user-modePhilippe Mathieu-Daudé
2020-12-13target/mips: Replace magic values by CP0PM_MASK or TARGET_PAGE_BITS_MINPhilippe Mathieu-Daudé
2020-11-03target/mips: Fix Lesser GPL version numberChetan Pant
2020-01-29target/mips: Add implementation of GINVT instructionYongbok Kim
2019-10-25target/mips: Clean up helper.cAleksandar Markovic
2019-07-02qapi: Split machine-target.json off target.json and misc.jsonMarkus Armbruster
2019-06-10target/mips: Use env_cpu, env_archcpuRichard Henderson
2019-05-26mips: Decide to map PAGE_EXEC in map_addressJakub Jermář
2019-05-10tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson
2019-05-10target/mips: Convert to CPUClass::tlb_fillRichard Henderson
2019-05-10target/mips: Tidy control flow in mips_cpu_handle_mmu_faultRichard Henderson
2019-05-10target/mips: Pass a valid error to raise_mmu_exception for user-onlyRichard Henderson
2019-02-21target/mips: implement QMP query-cpu-definitions commandPavel Dovgalyuk
2019-02-14target/mips: reimplement SC instruction emulation and use cmpxchgLeon Alrae
2018-10-18target/mips: Implement hardware page table walker for MIPS32Yongbok Kim
2018-08-24target/mips: Add updating BadInstr and BadInstrX for nanoMIPSStefan Markovic
2018-08-16target/mips: Don't update BadVAddr register in Debug ModeYongbok Kim
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier
2017-09-21mips: introduce internal.h and cleanup cpu.hPhilippe Mathieu-Daudé
2017-08-02mips: Add KVM T&E segment support for TCGJames Hogan
2017-08-02mips: Improve segment defs for KVM T&E guestsJames Hogan
2017-07-20target/mips: Implement segmentation controlJames Hogan
2017-07-20target/mips: Check memory permissions with mem_idxJames Hogan
2017-07-20target/mips: Add CP0_Ebase.WG (write gate) supportJames Hogan
2017-07-20target/mips: Weaken TLB flush on UX,SX,KX,ASID changesJames Hogan
2017-07-17mips: set CP0 Debug DExcCode for SDBBP instructionPavel Dovgalyuk
2017-03-20target-mips: fix compiler warnings (clang 5)Philippe Mathieu-Daudé
2017-01-13cputlb: drop flush_global flag from tlb_flushAlex Bennée
2016-12-20Move target-* CPU file into a target/ folderThomas Huth