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path: root/target/microblaze/translate.c
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2018-06-15target-microblaze: Rework NOP/zero instruction handlingEdgar E. Iglesias
Remove the abort on a sequence of NOP/zero instructions. Always return early and avoid decoding NOP/zero instructions. This fixes Coverity CID 1391443. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson
Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more sanity checking of the index argument. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-29target-microblaze: Use tcg_gen_movcond in eval_cond_jmpEdgar E. Iglesias
Cleanup eval_cond_jmp to use tcg_gen_movcond_i64(). No functional change. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Convert env_btarget to i64Edgar E. Iglesias
Convert env_btarget to i64. No functional change. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Remove argument b in eval_cc()Edgar E. Iglesias
Remove argument b in eval_cc() as it is always set to zero. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Use table based condition-codes conversionEdgar E. Iglesias
Use a table based conversion to map condition-codes between MicroBlaze ISA encoding and TCG. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Simplify address computation using tcg_gen_addi_i32()Edgar E. Iglesias
Simplify address computation using tcg_gen_addi_i32(). tcg_gen_addi_i32() already optimizes the case when the immediate is zero. No functional change. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Add support for extended access to TLBLOEdgar E. Iglesias
Add support for extended access to TLBLO's upper 32 bits. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: dec_msr: Plug a temp leakEdgar E. Iglesias
Plug a temp leak. Reported-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Implement MFSE EAREdgar E. Iglesias
Implement MFSE EAR to enable access to the upper part of EAR. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Add Extended AddressingEdgar E. Iglesias
Add support for Extended Addressing. Load/stores with EA enabled concatenate two 32bit registers to form an extended address. We don't allow users to enable address sizes larger than 32 bits quite yet though. Once the MMU support is in, we'll turn it on. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Make special registers 64-bitEdgar E. Iglesias
Extend special registers to 64-bits. This is in preparation for MFSE/MTSE, moves to and from extended special registers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: dec_msr: Fix MTS to FSREdgar E. Iglesias
Fix moves to FSR. Not only bit 31 is accessible. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: dec_msr: Reuse more code when reg-decodingEdgar E. Iglesias
Reuse more code when decoding register numbers. No functional changes. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: dec_msr: Use bool and extract32Edgar E. Iglesias
Use bool and extract32 to represent the to, clr and clrset flags. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Break out trap_illegal()Edgar E. Iglesias
Break out trap_illegal() to handle illegal operation traps. We now generally stop translation of the current insn if it's not valid. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Break out trap_userspace()Edgar E. Iglesias
Break out trap_userspace() to avoid open coding it everywhere. For privileged insns, we now always stop translation of the current insn for cores without exceptions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Name special registers we supportEdgar E. Iglesias
Name special registers we support. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Use TCGv for load/store addressesEdgar E. Iglesias
Use TCGv for load/store addresses, allowing for future computation of 64-bit load/store address. No functional change. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Remove pointer indirection for ld/st addressesEdgar E. Iglesias
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Make compute_ldst_addr always use a tempEdgar E. Iglesias
Make compute_ldst_addr always use a temp. This simplifies the code a bit in preparation for adding support for 64bit addresses. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Tighten up TCGv_i32 vs TCGv type usageEdgar E. Iglesias
Tighten up TCGv_i32 vs TCGv type usage. Avoid using TCGv when TCGv_i32 should be used. This is in preparation for adding 64bit addressing support. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: Correct special register array sizesEdgar E. Iglesias
Correct special register array sizes. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: compute_ldst_addr: Use bool instead of intEdgar E. Iglesias
Use bool instead of int to represent flags. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: dec_store: Use bool instead of unsigned intEdgar E. Iglesias
Use bool instead of unsigned int to represent flags. Also, use extract32 instead of open coding the bit extract. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-29target-microblaze: dec_load: Use bool instead of unsigned intEdgar E. Iglesias
Use bool instead of unsigned int to represent flags. No functional change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-05-09target/microblaze: avoid integer overflow in next_page PC checkEmilio G. Cota
If the PC is in the last page of the address space, next_page_start overflows to 0. Fix it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-04-30target-microblaze: Don't clobber the IMM reg for ld/st reversedEdgar E. Iglesias
Do not clobber the IMM register on reversed load/stores. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-04-30target-microblaze: Fix trap checks for FPU insnsEdgar E. Iglesias
Fix trap checks for FPU insns when extended FPU insns are enabled. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2018-04-30target-microblaze: Respect MSR.PVR as read-onlyEdgar E. Iglesias
Respect MSR.PVR as read-only. We were wrongly overwriting the PVR bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-12-29tcg: Dynamically allocate TCGOpsRichard Henderson
With no fixed array allocation, we can't overflow a buffer. This will be important as optimizations related to host vectors may expand the number of ops used. Use QTAILQ to link the ops together. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell
Capstone disassembler # gpg: Signature made Thu 26 Oct 2017 10:57:27 BST # gpg: using RSA key 0x64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-dis-20171026: disas: Add capstone as submodule disas: Remove monitor_disas_is_physical ppc: Support Capstone in disas_set_info arm: Support Capstone in disas_set_info i386: Support Capstone in disas_set_info disas: Support the Capstone disassembler library disas: Remove unused flags arguments target/arm: Don't set INSN_ARM_BE32 for CONFIG_USER_ONLY target/arm: Move BE32 disassembler fixup target/ppc: Convert to disas_set_info hook target/i386: Convert to disas_set_info hook Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # target/i386/cpu.c # target/ppc/translate_init.c
2017-10-25disas: Remove unused flags argumentsRichard Henderson
Now that every target is using the disas_set_info hook, the flags argument is unused. Remove it. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson
This is identical for each target. So, move the initialization to common code. Move the variable itself out of tcg_ctx and name it cpu_env to minimize changes within targets. This also means we can remove tcg_global_reg_new_{ptr,i32,i64}, since there are no longer global-register temps created by targets. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota
Groundwork for supporting multiple TCG contexts. The core of this patch is this change to tcg/tcg.h: > -extern TCGContext tcg_ctx; > +extern TCGContext tcg_init_ctx; > +extern TCGContext *tcg_ctx; Note that for now we set *tcg_ctx to whatever TCGContext is passed to tcg_context_init -- in this case &tcg_init_ctx. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota
Convert all existing readers of tb->cflags to tb_cflags, so that we use atomic_read and therefore avoid undefined behaviour in C11. Note that the remaining setters/getters of the field are protected by tb_lock, and therefore do not need conversion. Luckily all readers access the field via 'tb->cflags' (so no foo.cflags, bar->cflags in the code base), which makes the conversion easily scriptable: FILES=$(git grep 'tb->cflags' target include/exec/gen-icount.h \ accel/tcg/translator.c | cut -f1 -d':' | sort | uniq) perl -pi -e 's/([^.>])tb->cflags/$1tb_cflags(tb)/g' $FILES perl -pi -e 's/([a-z->.]*)(->|\.)tb->cflags/tb_cflags($1$2tb)/g' $FILES Then manually fixed the few errors that checkpatch reported. Compile-tested for all targets. Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova
Used later. An enum makes expected values explicit and bounds the value space of switches. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <150002049746.22386.2316077281615710615.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-01microblaze: replace cpu_mb_init() with cpu_generic_init()Igor Mammedov
cpu_mb_init() always falls back to TYPE_MICROBLAZE_CPU object regardless of cpu_model. Put fallback logic into mb_cpu_class_by_name() which would translate any cpu_model into TYPE_MICROBLAZE_CPU class and replace cpu_mb_init() with cpu_generic_init(). Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1503592308-93913-13-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova
Needed to implement a target-agnostic gen_intermediate_code() in the future. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-04target-microblaze: dec_barrel: Add BSIFIEdgar E. Iglesias
Add support for BSIFI. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-07-04target-microblaze: dec_barrel: Add BSEFIEdgar E. Iglesias
Add support for BSEFI. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-07-04target-microblaze: dec_barrel: Plug TCG temp leakEdgar E. Iglesias
Plug TCG temp leak. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-07-04target-microblaze: dec_barrel: Add braces around if-statementsEdgar E. Iglesias
Add braces around if-statements. No functional change. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-07-04target-microblaze: dec_barrel: Use extract32Edgar E. Iglesias
Use extract32 instead of opencoding the shifting and masking. No functional change. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-07-04target-microblaze: dec_barrel: Use bool instead of unsigned intEdgar E. Iglesias
Use bool instead of unsigned int to represent flags. No functional change. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-07-04target-microblaze: Introduce a use-pcmp-instr propertyEdgar E. Iglesias
Introduce a use-pcmp-instr property making pcmp instructions optional. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-07-04target-microblaze: Introduce a use-msr-instr propertyEdgar E. Iglesias
Introduce a use-msr-instr property making msr instructions optional. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-07-04target-microblaze: Introduce a use-hw-mul propertyEdgar E. Iglesias
Introduce a use-div property making multiplication instructions optional. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-07-04target-microblaze: Introduce a use-div propertyEdgar E. Iglesias
Introduce a use-div property making division instructions optional. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-07-04target-microblaze: Introduce a use-barrel propertyEdgar E. Iglesias
Introduce a use-barrel property making barrel shifter instructions optional. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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